ROSE  0.11.50.0
InstructionEnumsAarch64.h
1 #ifndef ROSE_BinaryAnalysis_InstructionEnumsAarch64_H
2 #define ROSE_BinaryAnalysis_InstructionEnumsAarch64_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_ASM_AARCH64
5 
6 #include <capstone/arm64.h>
7 #include <string>
8 
9 namespace Rose {
10 namespace BinaryAnalysis {
11 
12 using ::arm64_insn;
13 using Aarch64InstructionKind = ::arm64_insn;
15 using ::arm64_cc;
16 using Aarch64InstructionCondition = ::arm64_cc;
18 using ::arm64_extender;
19 using Aarch64Extender = ::arm64_extender;
21 using ::arm64_vas;
22 using Aarch64VectorArrangement = ::arm64_vas;
24 using ::arm64_at_op;
25 using Aarch64AtOperation = ::arm64_at_op;
27 using ::arm64_prefetch_op;
28 using Aarch64PrefetchOperation = ::arm64_prefetch_op;
30 using ::arm64_barrier_op;
31 using Aarch64BarrierOperation = ::arm64_barrier_op;
34 enum class Aarch64Exception {
35  brk
36 };
37 
40  aarch64_regclass_gpr,
41  aarch64_regclass_sp,
42  aarch64_regclass_ext,
43  aarch64_regclass_pc,
44  aarch64_regclass_cc,
45  aarch64_regclass_system,
46 };
47 
55  aarch64_system_actlr = 0, // auxiliary control registers
56  aarch64_system_ccsidr = 4, // current cache size ID registers
57  aarch64_system_clidr = 8, // cache level ID registers
58  aarch64_system_cntfrq = 12, // counter-timer frequency registers
59  aarch64_system_cntpct = 16, // counter-timer physical count registers
60  aarch64_system_cntkctl = 20, // counter-timer kernel control registers
61  aarch64_system_cntp_cval = 24, // counter-timer physical timer compare registers
62  aarch64_system_cpacr = 28, // coprocessor access control registers
63  aarch64_system_csselr = 32, // cache size selection registers
64  aarch64_system_cntp_ctl = 36, // counter-timer physical control registers
65  aarch64_system_ctr = 40, // cache type registers
66  aarch64_system_dczid = 44, // data cache zero ID registers
67  aarch64_system_elr = 48, // exception link registers
68  aarch64_system_esr = 52, // exception syndrome registers
69  aarch64_system_far = 56, // fault address registers
70  aarch64_system_hcr = 60, // hypervisor configuration registers
71  aarch64_system_mair = 64, // memory attribute indirection registers
72  aarch64_system_midr = 68, // main ID registers
73  aarch64_system_mpidr = 72, // multiprocessor affinity registers
74  aarch64_system_scr = 76, // secure configuration registers
75  aarch64_system_sctlr = 80, // system control registers
76  aarch64_system_spsr = 84, // saved program status registers
77  aarch64_system_tcr = 88, // translation control registers
78  aarch64_system_tpidr = 92, // user read/write thread ID registers
79  aarch64_system_tpidrr0 = 96, // user read-only thread ID registers
80  aarch64_system_ttbr0 = 100, // translation table base registers 0
81  aarch64_system_ttbr1 = 104, // translation table base register 1
82  aarch64_system_vbar = 108, // vector based address registers
83  aarch64_system_vtcr = 112, // virtualization translation control registers
84  aarch64_system_vttbr = 116 // virtualization translation table base registers
85 };
86 
87 } // namespace
88 } // namespace
89 
90 #endif
91 #endif
const char * Aarch64RegisterClass(int64_t)
Convert Rose::BinaryAnalysis::Aarch64RegisterClass enum constant to a string.
Definition: stringify.C:41355
Main namespace for the ROSE library.
const char * Aarch64SystemRegisters(int64_t)
Convert Rose::BinaryAnalysis::Aarch64SystemRegisters enum constant to a string.
Definition: stringify.C:41413