ROSE  0.9.12.19
InstructionEnumsM68k.h
1 #ifndef ROSE_BinaryAnalysis_InstructionEnumsM68k_H
2 #define ROSE_BinaryAnalysis_InstructionEnumsM68k_H
3 /* References:
4  * [1] "M68000 PM/AD REV.1 Programmers Reference Manual (Includes CPU32 Instructions)" Downloaded from the
5  * Freescale website on 2013-10-07.
6  */
7 
8 namespace Rose {
9 namespace BinaryAnalysis {
10 
15 enum M68kFamily {
16  m68k_family = 0xffffffff,
17  // Generation one (internally 16/32-bit and produced with 8-, 16-, and 32-bit interfaces)
18  m68k_generation_1 = 0x000000ff,
19  m68k_68000_only = 0x00000001,
20  m68k_68ec000 = 0x00000002,
21  m68k_68hc000 = 0x00000004,
22  m68k_68000 = 0x00000007,
23  m68k_68008 = 0x00000008,
24  m68k_68010 = 0x00000010,
25  m68k_68012 = 0x00000020,
26  // Generation two (internally fully 32-bit)
27  m68k_generation_2 = 0x0000ff00,
28  m68k_68020_only = 0x00000100,
29  m68k_68ec020 = 0x00000200,
30  m68k_68020 = 0x00000300,
31  m68k_68030_only = 0x00000400,
32  m68k_68ec030 = 0x00001000,
33  m68k_68030 = 0x00002000,
34  // Generation three (pipelined)
35  m68k_generation_3 = 0x00ff0000,
36  m68k_68040_only = 0x00010000,
37  m68k_68ec040 = 0x00020000,
38  m68k_68lc040 = 0x00040000,
39  m68k_68040 = 0x00070000,
40  // Freescale CPUs based on m68k
41  m68k_freescale = 0xff000000,
42  m68k_freescale_cpu32= 0x01000000,
43  m68k_freescale_isaa = 0x02000000,
44  m68k_freescale_isab = 0x04000000,
45  m68k_freescale_isac = 0x08000000,
46  m68k_freescale_fpu = 0x10000000,
47  m68k_freescale_mac = 0x20000000,
48  m68k_freescale_emac = 0x40000000,
49  m68k_freescale_emacb= 0x80000000
50 };
51 
60 };
61 
69 };
70 
85 };
86 
95 };
96 
124 };
125 
186  m68k_eam_unknown = 0,
187 
188  // single bits
189  m68k_eam_drd = 0x00000001,
190  m68k_eam_ard = 0x00000002,
191  m68k_eam_ari = 0x00000004,
192  m68k_eam_inc = 0x00000008,
193  m68k_eam_dec = 0x00000010,
194  m68k_eam_dsp = 0x00000020,
195  m68k_eam_idx8 = 0x00000040,
196  m68k_eam_idxbd = 0x00000080,
197  m68k_eam_mpost = 0x00000100,
198  m68k_eam_mpre = 0x00000200,
199  m68k_eam_pcdsp = 0x00000400,
200  m68k_eam_pcidx8 = 0x00000800,
201  m68k_eam_pcidxbd = 0x00001000,
202  m68k_eam_pcmpost = 0x00002000,
203  m68k_eam_pcmpre = 0x00004000,
204  m68k_eam_absw = 0x00008000,
205  m68k_eam_absl = 0x00010000,
206  m68k_eam_imm = 0x00020000,
208  // masks for groups of rows from the table above.
209  m68k_eam_all = 0x0003ffff,
210  m68k_eam_rd = 0x00000003,
211  m68k_eam_ri = 0x0000003c,
212  m68k_eam_idx = 0x000000c0,
213  m68k_eam_mi = 0x00000300,
214  m68k_eam_pci = 0x00000400, // NO_STRINGIFY
215  m68k_eam_pcidx = 0x00001800,
216  m68k_eam_pcmi = 0x00006000,
217  m68k_eam_abs = 0x00018000,
219  // masks for the data, mem, ctl, alter, and 234 columns of the table above.
220  m68k_eam_data = 0x0003fffd,
221  m68k_eam_memory = 0x0003fffc,
222  m68k_eam_control = 0x0001ffe4,
224  m68k_eam_alter = 0x0001e3ff,
229  m68k_eam_234 = 0x00007380,
231  // additional useful masks
232  m68k_eam_direct = 0x00000003, // NO_STRINGIFY
233  m68k_eam_pc = 0x00007c00
234 };
235 
248 };
249 
252  m68k_unknown_instruction,
283 // m68k_bfffo, /**< Find first one in bit field */
287 // m68k_bitrev, /**< Bit reverse register */
293 // m68k_byterev, /**< Byte reverse register */
377 // m68k_ff1, /**< Find first one in register */
385 // m68k_frestore,
388 // m68k_fsave,
398 // m68k_halt, /**< Halt the CPU */
400 // m68k_intouch,
437 // m68k_pulse, /**< Generate unique processor status */
438 // m68k_rems, /**< Signed divide remainder -- see divs instead */
439 // m68k_remu, /**< Unsigned divide remainder -- see divu instead */
446 // m68k_rte, /**< Return from exception */
449 // m68k_sats, /**< Signed saturate */
467 // m68k_stop,
475 // m68k_tpf, /**< Trap false (no operation) */
497 // m68k_wddata, /**< Write to debug data */
498 // m68k_wdebug,
499 
500  // must be last
501  m68k_last_instruction
502 };
503 
504 } // namespace
505 } // namespace
506 
507 #endif
Freescale CPU32 (similar to MC68020 w/out bitfield insns.
RAM 0 permutation control register 2.
Signed divide 32-bit quotient with remainder.
MC68EC000 16-/32-bit embedded controller.
Address register indirect with pre decrement: -(An)
Floating-point integer part rounded-to-zero.
Floating-point negation with single-precision rounding.
Access control register 2 (instruction).
Unsigned divide with optional remainder.
Floating-point branch if unordered or greater than.
Address register indirect: (An)
Memory indirect pre indexed.
MC68040 third-generation 32-bit microprocessor.
Freescale ISA_B, improved data movement instructions, etc.
RAM 0 permutation control register 3.
Floating-point branch if unordered or greater than or equal.
Decrement and branch if equal.
MC68020 32-bit virtual memory microprocessor.
Move floating-point data with single-precision rounding.
Status register, including condition codes.
M68kInstructionKind
M68k instruction types.
Floating-point branch if greater or less than.
Decrement and branch if less than.
Floating-point control register.
MC68010 16-/32-bit virtual memory microprocessor.
Secondary module base address register.
Compare and swap with operands.
Module base address register.
Floating-point branch if not greater or less than.
Floating-point branch if signaling not equal.
Test bit field and change.
Floating-point branch if false.
Multiprocessor control register.
Floating-point branch if unordered.
Move from source to destination (data, CCR, ACC, MACSR, MASK)
Unpack binary coded decimal.
Program counter indirect with index.
Multiply-accumulate registers (includes EMAC registers).
Take illegal instruction trap.
Floating-point square root with FPCR rounding.
MC68EC020 32-bit embedded controller.
Negate decimal with extend.
M68kSupervisorRegister
M68k supervisor registers.
Branch carry set (alias blo)
RAM 0 permutation control register 1.
MC68000 and embedded versions thereof.
Freescale EMAC_B, dual accumulation instructions.
Floating-point multiple with double-precision rounding.
Move condition code register.
Program counter indirect with displacement: (d_16,PC)
Floating-point subtract with single-precision rounding.
Embedded DRAM base address register.
Freescale ISA_A, the original ColdFire ISA (subset of M68000)
Move floating-point data with FPCR rounding.
Subtract decimal with extend.
M68kEmacRegister
M68k EMAC registers.
Freescale CPUs based on Motorola 683xx.
Floating-point subtract with double-precision rounding.
Floating-point divide with single-precision rounding.
Floating-point branch if not equal.
Main namespace for the ROSE library.
Register direct addressing modes.
Decrement and branch if lower or same.
Interrupt vector base address.
Floating-point add with FPCR rounding.
Extract bit field unsigned.
Decrement and branch if greater or equal.
Floating-point multiply with single-precision rounding.
Floating-point multiply with FPCR rounding.
MC68020 and embedded versions thereof.
Memory indirect addressing modes.
MC68040 and embedded versions thereof.
Branch carry clear (alias bhs)
Floating-point no operation.
Decrement and branch if greater than.
M68kDataFormat
M68k data formats for floating-point operations.
Move address from source to destination.
Check register against bounds.
Floating-point branch if signaling equal.
Floating-point branch if ordered greater than.
Floating-point branch if equal.
Floating-point branch if greater than or equal.
MC68008 16-bit microprocessor with 8-bit external data bus.
Floating-point add with double-precision rounding.
Access control register 1 (data).
Floating-point branch if true.
Address register indirect with displacement: (d_16,An)
Signed divide with optional remainder.
Check register against bounds.
Floating-point branch if not greater than.
Addressing modes specific to m680{20,30,40}.
M68kRegisterClass
M68k register classes.
Floating-point branch if unordered or equal.
Decrement and branch if cary clear.
Floating-point branch if ordered greater than or equal.
M68kFamily
Members of the Motorola Coldfire family of m68k processors.
Program counter indirect with scaled index and base displacement.
Floating-point negation with double-precision rounding.
Decrement and branch if overflow clear.
Freescale EMAC, enhanced multiply-accumulate ISA.
RAM 1 permutation control register 3.
Freescale FPU, original ColdFire floating point ISA.
Floating-point absolute value with double-precision rounding.
Move floating-point data with double-precision rounding.
M68kSpecialPurposeRegister
M68k special purpose registers.
Freescale ISA_C, improved bit manipulation instructions.
Floating-point square root with double-precision rounding.
MC68LC040 32-bit embedded controller w/out FPU.
Three 32-bit words of binary coded decimal.
Extensions for ACC2 and ACC3.
Floating-point divide with FPCR rounding.
Freescale MAC, original ColdFire multiply-accumulate ISA.
Floating-point branch if not less than.
RAM 1 permutation control register 1.
Decrement and branch if plus.
Floating-point branch if signaling true.
Rotate right without extend.
Sign extend byte to longword.
64-bit floating point, "double real".
Push and invalidate cache pages.
Memory indirect post indexed.
Program counter memory indirect post indexed.
M68kMacRegister
M68k MAC registers.
Floating-point branch if less than or equal.
Floating-point instruction address register.
32-bit floating point, "single real".
Rotate right with extend.
MC68EC040 32-bit embedded controller w/out FPU or MMU.
Address register indirect with post increment: (An)+.
Access control register 0 (data).
Access control register 3 (instruction).
MC68000 16-/32-bit microprocessor.
Floating-point branch if not less than or equal.
Decrement and branch if overflow set.
Floating-point branch if less than.
Floating-point add with single-precision rounding.
Floating-point branch if signaling false.
Address register indirect with scaled index and base displacement.
Floating-point branch if unordered or less or equal.
Decrement and branch if not equal.
Decrement and branch if less than or equal.
Unsigned divide 32-bit quotient with remainder.
Register indirect addressing modes.
Compare and swap with operand.
Floating-point subtract with FPCR rounding.
MC68012 84-pin PGA version of MC68010 supporting 2GB RAM.
Address register direct: An.
Extensions for ACC0 and ACC1.
Program counter memory indirect.
Floating-point branch if greater than.
96-bit floating point, "extended real".
Absolute data addressing long: (xxx).L.
RAM 1 permutation control register 2.
Rotate left without extend.
Move from MAC ACC register and clear.
MC68030 and embedded versions thereof.
Floating-point branch if ordered less than or equal.
Decrement and branch if true.
Push and invalidate cache lines.
MC68EC030 32-bit embedded controller.
Address register indirect with scaled index.
MC68030 second-generation 32-bit enhanced microprocessor.
Floating-point branch if not greater, less, or equal.
Floating-point branch if greater, less, or equal.
Floating-point branch if ordered.
MC68HC000 low-power CMOS version of MC68000.
Floating-point absolute value with single-precision rounding.
Decrement and branch if high.
Return and restore condition codes.
Floating-point integer part.
Floating-point divide with double-precision rounding.
Floating-point branch if not greater than or equal.
Move multiple floating-point data registers.
Floating-point branch if unordered less than.
All register direct addressing modes.
Floating-pont negate with FPCR rounding.
Decrement and branch if false.
Floating-point absolute value with FPCR rounding.
Compare register against bounds.
M68kEffectiveAddressMode
M68k effective addressing modes.
Floating-point branch if ordered greater or less than.
Address register indirect with scaled index and 8-bit displacement.
Floating-point branch if ordered less than.
Floating-point status register.
Floating-point square root with single-precision rounding.
Decrement and branch if carry set.
Absolute data addressing short: (xxx).W.
Program counter indirect with scaled index and 8-bit displacement.
Add decimal with extended.
Program counter memory indirect pre indexed.
Decrement and branch if minus.