AssemblerX86.h

/* Assembly specific to the x86 architecture. */
 
#ifndef ROSE_BinaryAnalysis_AssemblerX86_H
#define ROSE_BinaryAnalysis_AssemblerX86_H
 
#include <featureTests.h>
#ifdef ROSE_ENABLE_BINARY_ANALYSIS
#include "Assembler.h"
 
#include <Rose/BinaryAnalysis/InstructionEnumsX86.h>
 
namespace Rose {
namespace BinaryAnalysis {
 
class AssemblerX86: public Assembler {
public:
    AssemblerX86()
        : honor_operand_types(false) {
        if (defns.size()==0)
            initAssemblyRules();
    }
 
    virtual ~AssemblerX86() {}
 
    virtual SgUnsignedCharList assembleOne(SgAsmInstruction*);
    
    void set_honor_operand_types(bool b) {
        honor_operand_types = b;
    }
 
    bool get_honor_operand_types() const {
        return honor_operand_types;
    }
 
    virtual SgUnsignedCharList assembleProgram(const std::string &source);
 
    /*========================================================================================================================
     * Members for defining instructions.
     *========================================================================================================================*/
private:
    /* These bit masks specify how the opcode part of the encoding is generated. The base opcode bytes are specified with
     * a 64-bit value so that up to eight bytes of opcode can be specified.  The bytes generated come from the 64-bit opcode
     * value in big-endian order but without leading zero bytes. If the 64-bit opcode is zero then a single zero byte is
     * generated.  For instance, the MONITOR instruction has an opcode of 0x0f01c8, generating the encoding 0x0f, 0x01, 0xc8. */
    
    static const unsigned od_e_mask   = 0x00000070;                /* mask for numeric value (n) part of En field. */
    static const unsigned od_e_pres   = 0x00000080;                /* bit set if En modification was specified. */
    static const unsigned od_e0       = 0x00000000 | od_e_pres;
    static const unsigned od_e1       = 0x00000010 | od_e_pres;
    static const unsigned od_e2       = 0x00000020 | od_e_pres;
    static const unsigned od_e3       = 0x00000030 | od_e_pres;
    static const unsigned od_e4       = 0x00000040 | od_e_pres;
    static const unsigned od_e5       = 0x00000050 | od_e_pres;
    static const unsigned od_e6       = 0x00000060 | od_e_pres;
    static const unsigned od_e7       = 0x00000070 | od_e_pres;
    static size_t od_e_val(unsigned opcode_mods) { return (opcode_mods & od_e_mask)>>4; } 
    static const unsigned od_rex_pres = 0x00000001;                /* bit set if REX prefix is present. */
    static const unsigned od_rex_mask = 0x00000f00;                /* mask for low nyble of REX byte. */
    static const unsigned od_rex      = 0x00000000 | od_rex_pres;
    static const unsigned od_rexb     = 0x00000100 | od_rex_pres;
    static const unsigned od_rexx     = 0x00000200 | od_rex_pres;
    static const unsigned od_rexxb    = 0x00000300 | od_rex_pres;
    static const unsigned od_rexr     = 0x00000400 | od_rex_pres;
    static const unsigned od_rexrb    = 0x00000500 | od_rex_pres;
    static const unsigned od_rexrx    = 0x00000600 | od_rex_pres;
    static const unsigned od_rexrxb   = 0x00000700 | od_rex_pres;
    static const unsigned od_rexw     = 0x00000800 | od_rex_pres;
    static const unsigned od_rexwb    = 0x00000900 | od_rex_pres;
    static const unsigned od_rexwx    = 0x00000a00 | od_rex_pres;
    static const unsigned od_rexwxb   = 0x00000b00 | od_rex_pres;
    static const unsigned od_rexwr    = 0x00000c00 | od_rex_pres;
    static const unsigned od_rexwrb   = 0x00000d00 | od_rex_pres;
    static const unsigned od_rexwrx   = 0x00000e00 | od_rex_pres;
    static const unsigned od_rexwrxb  = 0x00000f00 | od_rex_pres;
    static uint8_t od_rex_byte(unsigned opcode_mods) { return 0x40 | ((opcode_mods & od_rex_mask) >> 8); }
 
    static const unsigned od_modrm    = 0x00000002;
 
    static const unsigned od_c_mask   = 0x00007000;
    static const unsigned od_cb       = 0x00001000;
    static const unsigned od_cw       = 0x00002000;
    static const unsigned od_cd       = 0x00003000;
    static const unsigned od_cp       = 0x00004000;
    static const unsigned od_co       = 0x00005000;
    static const unsigned od_ct       = 0x00006000;
 
    static const unsigned od_i_mask   = 0x00070000;
    static const unsigned od_ib       = 0x00010000;
       static const unsigned od_iw       = 0x00020000;
    static const unsigned od_id       = 0x00030000;
    static const unsigned od_io       = 0x00040000;
 
    static const unsigned od_r_mask   = 0x00700000;
    static const unsigned od_rb       = 0x00100000;
    static const unsigned od_rw       = 0x00200000;
    static const unsigned od_rd       = 0x00300000;
    static const unsigned od_ro       = 0x00400000;
 
    static const unsigned od_i        = 0x00000004;
 
 
    enum OperandDefn 
        {
        od_none,        
        od_AL,          
        od_AX,          
        od_EAX,         
        od_RAX,         
        od_DX,          
        od_CS,          
        od_DS,          
        od_ES,          
        od_FS,          
        od_GS,          
        od_SS,          
        od_rel8,        
        od_rel16,       
        od_rel32,       
        od_rel64,       
        od_ptr16_16,    
        od_ptr16_32,    
        od_ptr16_64,    
        od_r8,          
        od_r16,         
        od_r32,         
        od_r64,         
        od_imm8,        
        od_imm16,       
        od_imm32,       
        od_imm64,       
        od_r_m8,        
        od_r_m16,       
        od_r_m32,       
        od_r_m64,       
        od_m,           
        od_m8,          
        od_m16,         
        od_m32,         
        od_m64,         
        od_m128,        
        od_m16_16,      
        od_m16_32,      
        od_m16_64,      
        od_m16a16,      
        od_m16a32,      
        od_m32a32,      
        od_m16a64,      
        od_moffs8,      
        od_moffs16,      
        od_moffs32,     
        od_moffs64,     
        od_sreg,        
        od_m32fp,       
        od_m64fp,       
        od_m80fp,       
        od_st0,         
        od_st1,         
        od_st2,         
        od_st3,         
        od_st4,         
        od_st5,         
        od_st6,         
        od_st7,         
        od_sti,         
        od_mm,          
        od_mm_m32,      
        od_mm_m64,      
        od_xmm,         
        od_xmm_m16,     
        od_xmm_m32,     
        od_xmm_m64,     
        od_xmm_m128,    
        /* The following are not documented in section 3.1.1.2 but are used elsewhere in the manual */
        od_XMM0,        
        od_0,           
        od_1,           
        od_m80,         
        od_dec,         
        od_m80bcd,      
        od_m2byte,      
        od_m14_28byte,  
        od_m94_108byte, 
        od_m512byte,    
        od_r16_m16,     
        od_r32_m8,      
        od_r32_m16,     
        od_r64_m16,     
        od_CR0,         
        od_CR7,         
        od_CR8,         
        od_CR0CR7,      
        od_DR0DR7,      
        od_reg,         
        od_CL,          
    };
 
    static const unsigned COMPAT_LEGACY = 0x01; 
    static const unsigned COMPAT_64     = 0x02; 
    static uint8_t build_modrm(unsigned mod, unsigned reg, unsigned rm) {
        return ((mod&0x3)<<6) | ((reg&0x7)<<3) | (rm&0x7);
    }
 
    static unsigned modrm_mod(uint8_t modrm) { return modrm>>6; }
 
    static unsigned modrm_reg(uint8_t modrm) { return (modrm>>3) & 0x7; }
 
    static unsigned modrm_rm(uint8_t modrm) { return modrm & 0x7; }
 
    static uint8_t build_sib(unsigned ss, unsigned index, unsigned base) {
        return ((ss&0x3)<<6) | ((index&0x7)<<3) | (base&0x7);
    }
 
    static unsigned sib_ss(uint8_t sib) {return sib>>6; }
 
    static unsigned sib_index(uint8_t sib) { return (sib>>3) & 0x7; }
 
    static unsigned sib_base(uint8_t sib) { return sib & 0x7; }
    
    class InsnDefn {
    public:
        InsnDefn(const std::string &mnemonic, X86InstructionKind kind, unsigned compatibility, uint64_t opcode,
                 unsigned opcode_modifiers, OperandDefn op1=od_none, OperandDefn op2=od_none, OperandDefn op3=od_none,
                 OperandDefn op4=od_none)
            : mnemonic(mnemonic), kind(kind), compatibility(compatibility), opcode(opcode), opcode_modifiers(opcode_modifiers) {
            if (op1) operands.push_back(op1);
            if (op2) operands.push_back(op2);
            if (op3) operands.push_back(op3);
            if (op4) operands.push_back(op4);
        }
        std::string to_str() const;
        void set_location(const std::string &s) {
            location = s;
        }
        std::string mnemonic;
        X86InstructionKind kind;
        unsigned compatibility;
        uint64_t opcode;
        unsigned opcode_modifiers;
        std::vector<OperandDefn> operands;
        std::string location;                           /* location of instruction documentation */
    };
 
    enum MemoryReferencePattern 
        {
        mrp_unknown,
        mrp_disp,                       /* displacement */
        mrp_index,                      /* register*scale */
        mrp_index_disp,                 /* register*scale + displacement */
        mrp_base,                       /* register */
        mrp_base_disp,                  /* register + displacement */
        mrp_base_index,                 /* register + register*scale */
        mrp_base_index_disp             /* register + register*scale + displacement */
    };
 
    typedef std::vector<const InsnDefn*> DictionaryPage;
 
    typedef std::map<X86InstructionKind, DictionaryPage> InsnDictionary;
 
    static void initAssemblyRules();
    static void initAssemblyRules_part1();
    static void initAssemblyRules_part2();
    static void initAssemblyRules_part3();
    static void initAssemblyRules_part4();
    static void initAssemblyRules_part5();
    static void initAssemblyRules_part6();
    static void initAssemblyRules_part7();
    static void initAssemblyRules_part8();
    static void initAssemblyRules_part9();
 
    static void define(const InsnDefn *d) {
        defns[d->kind].push_back(d);
    }
    
    static std::string to_str(X86InstructionKind);
 
    SgUnsignedCharList fixup_prefix_bytes(SgAsmX86Instruction *insn, SgUnsignedCharList source);
 
    SgUnsignedCharList assemble(SgAsmX86Instruction *insn, const InsnDefn *defn);
 
    void matches(const InsnDefn *defn, SgAsmX86Instruction *insn, int64_t *disp, int64_t *imm) const;
 
    bool matches(OperandDefn, SgAsmExpression*, SgAsmInstruction*, int64_t *disp, int64_t *imm) const;
 
    static bool matches_rel(SgAsmInstruction*, int64_t val, size_t nbytes);
        
    static MemoryReferencePattern parse_memref(SgAsmInstruction *insn, SgAsmMemoryReferenceExpression *expr,
                                               SgAsmRegisterReferenceExpression **base_reg/*out*/,
                                               SgAsmRegisterReferenceExpression **index_reg/*out*/,
                                               SgAsmValueExpression **scale/*out*/, SgAsmValueExpression **displacement/*out*/);
 
    uint8_t build_modrm(const InsnDefn*, SgAsmX86Instruction*, size_t argno,
                        uint8_t *sib, int64_t *displacement, uint8_t *rex) const;
 
    void build_modreg(const InsnDefn*, SgAsmX86Instruction*, size_t argno, uint8_t *modrm, uint8_t *rex) const;
 
    uint8_t segment_override(SgAsmX86Instruction*);
 
    static InsnDictionary defns;                
    bool honor_operand_types;                   
};
 
} // namespace
} // namespace
 
#endif
#endif