ROSE 0.11.145.147
Public Types | Public Member Functions | Static Public Member Functions | List of all members
Rose::BinaryAnalysis::Architecture::IntelPentium4 Class Reference

Description

Architecture-specific information for Intel Pentium4.

Pentium 4 is a series of single-core CPUs for desktops, laptops and entry-level servers manufactured by Intel. The processors were shipped from November 20, 2000 until August 8, 2008. It was removed from the official price lists starting in 2010, being replaced by Pentium Dual-Core.

All Pentium 4 CPUs are based on the NetBurst microarchitecture. The Pentium 4 Willamette (180 nm) introduced SSE2, while the Prescott (90 nm) introduced SSE3. Later versions introduced Hyper-Threading Technology (HTT).

The first Pentium 4-branded processor to implement 64-bit was the Prescott (90 nm) (February 2004), but this feature was not enabled. Intel subsequently began selling 64-bit Pentium 4s using the "E0" revision of the Prescotts, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the NX bit) to Intel

  1. Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott-2M.

Intel also marketed a version of their low-end Celeron processors based on the NetBurst microarchitecture (often referred to as Celeron 4), and a high-end derivative, Xeon, intended for multi-socket servers and workstations. In 2005, the Pentium 4 was complemented by the dual-core-brands Pentium D and Pentium Extreme Edition.

Definition at line 29 of file IntelPentium4.h.

#include <Rose/BinaryAnalysis/Architecture/IntelPentium4.h>

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Public Types

using Ptr = IntelPentium4Ptr
 
- Public Types inherited from Rose::BinaryAnalysis::Architecture::X86
using Ptr = X86Ptr
 
- Public Types inherited from Rose::BinaryAnalysis::Architecture::Base
using Ptr = BasePtr
 Reference counting pointer.
 
using ConstPtr = BaseConstPtr
 Reference counting pointer to const object.
 

Public Member Functions

RegisterDictionary::Ptr registerDictionary () const override
 Property: Register dictionary.
 
bool matchesHeader (SgAsmGenericHeader *) const override
 Tests whether this architecture matches a file header.
 
- Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::X86
virtual const CallingConvention::DictionarycallingConventions () const override
 Property: Calling convention definitions.
 
Sawyer::Container::Interval< size_t > bytesPerInstruction () const override
 Valid sizes for encoded machine instructions.
 
Alignment instructionAlignment () const override
 Alignment for encoded machine instructions.
 
std::string instructionMnemonic (const SgAsmInstruction *) const override
 Mnemonic for an instruction.
 
bool terminatesBasicBlock (SgAsmInstruction *) const override
 Determines whether the specified instruction normally terminates a basic block.
 
bool isUnknown (const SgAsmInstruction *) const override
 Returns true if the instruction is the special "unknown" instruction.
 
bool isFunctionCallFast (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override
 Returns true if the specified basic block looks like a function call.
 
bool isFunctionCallSlow (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override
 Returns true if the specified basic block looks like a function call.
 
bool isFunctionReturnFast (const std::vector< SgAsmInstruction * > &) const override
 Returns true if the specified basic block looks like a function return.
 
Sawyer::Optional< rose_addr_t > branchTarget (SgAsmInstruction *) const override
 Obtains the virtual address for a branching instruction.
 
AddressSet getSuccessors (SgAsmInstruction *, bool &complete) const override
 Control flow successors for a single instruction.
 
AddressSet getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete, const MemoryMapPtr &initial_memory=MemoryMapPtr()) const override
 Control flow successors for a basic block.
 
Disassembler::BasePtr newInstructionDecoder () const override
 Construct and return a new instruction decoder.
 
Unparser::BasePtr newUnparser () const override
 Construct and return a new instruction unparser.
 
virtual InstructionSemantics::BaseSemantics::DispatcherPtr newInstructionDispatcher (const InstructionSemantics::BaseSemantics::RiscOperatorsPtr &) const override
 Construct and return a new instruction dispatcher.
 
virtual std::vector< Partitioner2::FunctionPrologueMatcherPtrfunctionPrologueMatchers (const Partitioner2::EnginePtr &) const override
 Instruction patterns matching function prologues.
 
virtual std::vector< Partitioner2::BasicBlockCallbackPtrbasicBlockCreationHooks (const Partitioner2::EnginePtr &) const override
 Architecture-specific basic block callbacks for partitioning.
 
- Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base
const std::string & name () const
 Property: Architecture definition name.
 
ByteOrder::Endianness byteOrder () const
 Property: Byte order for memory.
 
virtual RegisterDictionaryPtr interruptDictionary () const
 Property: Interrupt dictionary.
 
virtual bool matchesName (const std::string &) const
 Tests whether this architecture matches a name.
 
bool instructionsCanOverlap () const
 Whether instructions can overlap in memory.
 
virtual std::string instructionDescription (const SgAsmInstruction *) const
 Description for an instruction.
 
const Sawyer::Optional< size_t > & registrationId () const
 Property: Registration identification number.
 
void registrationId (const Sawyer::Optional< size_t > &)
 Property: Registration identification number.
 
size_t bytesPerWord () const
 Property: Word size.
 
size_t bitsPerWord () const
 Property: Word size.
 
virtual std::string toString (const SgAsmInstruction *) const
 Unparse an instruction to a string.
 
virtual std::string toStringNoAddr (const SgAsmInstruction *) const
 Unparse an instruction to a string.
 
virtual bool isFunctionReturnSlow (const std::vector< SgAsmInstruction * > &) const
 Returns true if the specified basic block looks like a function return.
 
AddressSet getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete) const
 Control flow successors for a basic block.
 

Static Public Member Functions

static Ptr instance ()
 Allocating constructor.
 

Additional Inherited Members

- Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::X86
 X86 (const std::string &name, size_t bytesPerWord)
 
CallingConvention::Definition::Ptr cc_cdecl (size_t bitsPerWord) const
 
CallingConvention::Definition::Ptr cc_stdcall (size_t bitsPerWord) const
 
CallingConvention::Definition::Ptr cc_fastcall (size_t bitsPerWord) const
 
- Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base
 Base (const std::string &name, size_t bytesPerWord, ByteOrder::Endianness byteOrder)
 
Ptr ptr ()
 
ConstPtr constPtr () const
 
- Protected Attributes inherited from Rose::BinaryAnalysis::Architecture::Base
Sawyer::Cached< RegisterDictionaryPtrregisterDictionary_
 
Sawyer::Cached< RegisterDictionaryPtrinterruptDictionary_
 
Sawyer::Cached< CallingConvention::DictionarycallingConventions_
 
Sawyer::Cached< Unparser::Base::PtrinsnToString_
 
Sawyer::Cached< Unparser::Base::PtrinsnToStringNoAddr_
 

Member Typedef Documentation

◆ Ptr

using Rose::BinaryAnalysis::Architecture::IntelPentium4::Ptr = IntelPentium4Ptr

Definition at line 31 of file IntelPentium4.h.

Member Function Documentation

◆ registerDictionary()

RegisterDictionary::Ptr Rose::BinaryAnalysis::Architecture::IntelPentium4::registerDictionary ( ) const
overridevirtual

Property: Register dictionary.

The register dictionary defines a mapping between register names and register descriptors (RegisterDescriptor), and thus how the registers map into hardware.

Since dictionaries are generally not modified, it is permissible for this function to return the same dictionary every time it's called. The dictionary can be constructed on the first call.

Thread safety: Thread safe.

Implements Rose::BinaryAnalysis::Architecture::Base.

◆ matchesHeader()

bool Rose::BinaryAnalysis::Architecture::IntelPentium4::matchesHeader ( SgAsmGenericHeader ) const
overridevirtual

Tests whether this architecture matches a file header.

Returns true if this architecture matches the specified file header, and false otherwise.

The default implementation always returns false.

Reimplemented from Rose::BinaryAnalysis::Architecture::Base.


The documentation for this class was generated from the following file: