Description
Base class for architecture definitions.
Definition at line 22 of file Architecture/Base.h.
#include <Rose/BinaryAnalysis/Architecture/Base.h>
Public Types | |
| using | Ptr = BasePtr |
| Reference counting pointer. | |
| using | ConstPtr = BaseConstPtr |
| Reference counting pointer to const object. | |
Public Member Functions | |
| const std::string & | name () const |
| Property: Architecture definition name. | |
| ByteOrder::Endianness | byteOrder () const |
| Property: Byte order for memory. | |
| virtual RegisterDictionaryPtr | registerDictionary () const =0 |
| Property: Register dictionary. | |
| virtual RegisterDictionaryPtr | interruptDictionary () const |
| Property: Interrupt dictionary. | |
| virtual const CallingConvention::Dictionary & | callingConventions () const |
| Property: Calling convention definitions. | |
| virtual bool | matchesName (const std::string &) const |
| Tests whether this architecture matches a name. | |
| virtual bool | matchesHeader (SgAsmGenericHeader *) const |
| Tests whether this architecture matches a file header. | |
| virtual Disassembler::BasePtr | newInstructionDecoder () const =0 |
| Construct and return a new instruction decoder. | |
| virtual InstructionSemantics::BaseSemantics::DispatcherPtr | newInstructionDispatcher (const InstructionSemantics::BaseSemantics::RiscOperatorsPtr &) const |
| Construct and return a new instruction dispatcher. | |
| virtual Sawyer::Container::Interval< size_t > | bytesPerInstruction () const =0 |
| Valid sizes for encoded machine instructions. | |
| virtual Alignment | instructionAlignment () const =0 |
| Alignment for encoded machine instructions. | |
| bool | instructionsCanOverlap () const |
| Whether instructions can overlap in memory. | |
| virtual std::string | toString (const SgAsmExpression *) const |
| Unparse an expression to a string. | |
| virtual std::string | instructionMnemonic (const SgAsmInstruction *) const =0 |
| Mnemonic for an instruction. | |
| virtual std::string | instructionDescription (const SgAsmInstruction *) const |
| Description for an instruction. | |
| virtual bool | isUnknown (const SgAsmInstruction *) const =0 |
| Returns true if the instruction is the special "unknown" instruction. | |
| virtual bool | isControlTransfer (const SgAsmInstruction *) const |
| Returns true if the specified instruction is a control transfer instruction. | |
| virtual bool | terminatesBasicBlock (SgAsmInstruction *) const =0 |
| Determines whether the specified instruction normally terminates a basic block. | |
| virtual Sawyer::Optional< rose_addr_t > | branchTarget (SgAsmInstruction *) const |
| Obtains the virtual address for a branching instruction. | |
| virtual AddressSet | getSuccessors (SgAsmInstruction *, bool &complete) const |
| Control flow successors for a single instruction. | |
| virtual std::vector< Partitioner2::FunctionPrologueMatcherPtr > | functionPrologueMatchers (const Partitioner2::EnginePtr &) const |
| Instruction patterns matching function prologues. | |
| virtual std::vector< Partitioner2::BasicBlockCallbackPtr > | basicBlockCreationHooks (const Partitioner2::EnginePtr &) const |
| Architecture-specific basic block callbacks for partitioning. | |
| const Sawyer::Optional< size_t > & | registrationId () const |
| Property: Registration identification number. | |
| void | registrationId (const Sawyer::Optional< size_t > &) |
| Property: Registration identification number. | |
| size_t | bytesPerWord () const |
| Property: Word size. | |
| size_t | bitsPerWord () const |
| Property: Word size. | |
| virtual Unparser::BasePtr | newUnparser () const =0 |
| Construct and return a new instruction unparser. | |
| virtual Unparser::BasePtr | newInstructionUnparser () const |
| Construct and return a new instruction unparser. | |
| virtual std::string | toString (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual std::string | toStringNoAddr (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual bool | isFunctionCallFast (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const |
| Returns true if the specified basic block looks like a function call. | |
| virtual bool | isFunctionCallSlow (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const |
| Returns true if the specified basic block looks like a function call. | |
| virtual bool | isFunctionReturnFast (const std::vector< SgAsmInstruction * > &) const |
| Returns true if the specified basic block looks like a function return. | |
| virtual bool | isFunctionReturnSlow (const std::vector< SgAsmInstruction * > &) const |
| Returns true if the specified basic block looks like a function return. | |
| AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete) const |
| Control flow successors for a basic block. | |
| virtual AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete, const MemoryMapPtr &initial_memory) const |
| Control flow successors for a basic block. | |
Protected Member Functions | |
| Base (const std::string &name, size_t bytesPerWord, ByteOrder::Endianness byteOrder) | |
| Ptr | ptr () |
| ConstPtr | constPtr () const |
| virtual Unparser::BasePtr | insnUnparser () const |
Member Typedef Documentation
◆ Ptr
Reference counting pointer.
Definition at line 25 of file Architecture/Base.h.
◆ ConstPtr
Reference counting pointer to const object.
Definition at line 28 of file Architecture/Base.h.
Member Function Documentation
◆ name()
| const std::string & Rose::BinaryAnalysis::Architecture::Base::name | ( | ) | const |
Property: Architecture definition name.
The name is used for lookups, but it need not be unique since lookups prefer the latest registered architecture. I.e., if two architectures A, and B, have the same name, and B was registered after A, then lookup by the name will return architecture B.
A best practice is to use only characters that are not special in shell scripts since architecture names often appear as arguments to command-line switches. Also, try to use only lower-case letters, decimal digits and hyphens for consistency across all architecture names. See the list of ROSE built-in architecture names for ideas (this list can be obtained from many binary analysis tools, or the Architecture::registeredNames function).
Thread safety: Thread safe. The name is specified during construction and is thereafter read-only.
◆ registrationId() [1/2]
| const Sawyer::Optional< size_t > & Rose::BinaryAnalysis::Architecture::Base::registrationId | ( | ) | const |
Property: Registration identification number.
Architectures are identified by a small number that is automatically assigned when it is registered, and cleared when it is deregistered.
◆ registrationId() [2/2]
| void Rose::BinaryAnalysis::Architecture::Base::registrationId | ( | const Sawyer::Optional< size_t > & | ) |
Property: Registration identification number.
Architectures are identified by a small number that is automatically assigned when it is registered, and cleared when it is deregistered.
◆ bytesPerWord()
| size_t Rose::BinaryAnalysis::Architecture::Base::bytesPerWord | ( | ) | const |
Property: Word size.
This is the natural word size for the architecture, measured in bits or bytes (depending on the property name).
Thread safety: Thread safe. This property is set during construction and is thereafter read-only.
◆ bitsPerWord()
| size_t Rose::BinaryAnalysis::Architecture::Base::bitsPerWord | ( | ) | const |
Property: Word size.
This is the natural word size for the architecture, measured in bits or bytes (depending on the property name).
Thread safety: Thread safe. This property is set during construction and is thereafter read-only.
◆ byteOrder()
| ByteOrder::Endianness Rose::BinaryAnalysis::Architecture::Base::byteOrder | ( | ) | const |
Property: Byte order for memory.
When multi-byte values (such as 32-bit integral values) are stored in memory, this property is the order in which the value's bytes are stored. If the order is little endian, then the least significant byte is stored at the lowest address; if the order is big endian then the most significant byte is stored at the lowest address.
Thread safety: Thread safe. This property is set during construction and is thereafter read-only.
◆ registerDictionary()
|
pure virtual |
Property: Register dictionary.
The register dictionary defines a mapping between register names and register descriptors (RegisterDescriptor), and thus how the registers map into hardware.
Since dictionaries are generally not modified, it is permissible for this function to return the same dictionary every time it's called. The dictionary can be constructed on the first call.
Thread safety: Thread safe.
Implemented in Rose::BinaryAnalysis::Architecture::Amd64, Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Intel80286, Rose::BinaryAnalysis::Architecture::Intel8086, Rose::BinaryAnalysis::Architecture::Intel8088, Rose::BinaryAnalysis::Architecture::IntelI386, Rose::BinaryAnalysis::Architecture::IntelI486, Rose::BinaryAnalysis::Architecture::IntelPentium, Rose::BinaryAnalysis::Architecture::IntelPentium4, Rose::BinaryAnalysis::Architecture::IntelPentiumii, Rose::BinaryAnalysis::Architecture::IntelPentiumiii, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola68040, Rose::BinaryAnalysis::Architecture::NxpColdfire, Rose::BinaryAnalysis::Architecture::Powerpc32, and Rose::BinaryAnalysis::Architecture::Powerpc64.
◆ interruptDictionary()
|
virtual |
Property: Interrupt dictionary.
The interrupt dictionary (a kind of register dictionary) defines a mapping between interrupt names and descriptors (RegisterDescriptor), and thus how the interrupt names map to hardware. Interrupts are normally single-bit values that indicate whether the interrupt is in a raised or cleared state. Interrupts in ROSE have a major and minor number since they use the same addressing mechanism as registers.
Since dictionaries are generally not modified, it is permissible for this funtion to return the same dictionary every time it's called. The dictionary can be constructed on the first call.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Mips32.
◆ callingConventions()
|
virtual |
Property: Calling convention definitions.
Returns a list of calling convention definitions used by this architecture. Since definitions are generally not modified, it is permissible for this function to return the same definitions every time it's called. The list can be constructed on the first call.
The default implementation returns an empty list.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Amd64, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ matchesName()
|
virtual |
Tests whether this architecture matches a name.
Returns true if this architecture matches the specified name, and false otherwise.
The default implementation matches the name exactly, which is what one usually wants.
◆ matchesHeader()
|
virtual |
Tests whether this architecture matches a file header.
Returns true if this architecture matches the specified file header, and false otherwise.
The default implementation always returns false.
Reimplemented in Rose::BinaryAnalysis::Architecture::Amd64, Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Intel80286, Rose::BinaryAnalysis::Architecture::Intel8086, Rose::BinaryAnalysis::Architecture::Intel8088, Rose::BinaryAnalysis::Architecture::IntelI386, Rose::BinaryAnalysis::Architecture::IntelI486, Rose::BinaryAnalysis::Architecture::IntelPentium, Rose::BinaryAnalysis::Architecture::IntelPentium4, Rose::BinaryAnalysis::Architecture::IntelPentiumii, Rose::BinaryAnalysis::Architecture::IntelPentiumiii, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola68040, Rose::BinaryAnalysis::Architecture::NxpColdfire, Rose::BinaryAnalysis::Architecture::Powerpc32, and Rose::BinaryAnalysis::Architecture::Powerpc64.
◆ newInstructionDecoder()
|
pure virtual |
Construct and return a new instruction decoder.
Returns a new decoder for this architecture if possible, otherwise a null pointer.
Thread safety: Thread safe.
Implemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola68040, Rose::BinaryAnalysis::Architecture::NxpColdfire, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ newUnparser()
|
pure virtual |
Construct and return a new instruction unparser.
An unparser is responsible for generating pseudo assembly listings.
The newUnparser returns a default configured unparser suitable for unparsing instructions in the context of an assembly listing. The newInstructionUnparser returns a parser configured to show individual instructions showing only the instruction address, the instruction mnemonic, and the operands.
Example: The default instruction unparser uses color by default. If you want to turn off the color, you must create a new unparser, configure it to disable color, and then use it to unparse the instruction.
Thread safety: Thread safe.
Implemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ newInstructionUnparser()
|
virtual |
Construct and return a new instruction unparser.
An unparser is responsible for generating pseudo assembly listings.
The newUnparser returns a default configured unparser suitable for unparsing instructions in the context of an assembly listing. The newInstructionUnparser returns a parser configured to show individual instructions showing only the instruction address, the instruction mnemonic, and the operands.
Example: The default instruction unparser uses color by default. If you want to turn off the color, you must create a new unparser, configure it to disable color, and then use it to unparse the instruction.
Thread safety: Thread safe.
◆ newInstructionDispatcher()
|
virtual |
Construct and return a new instruction dispatcher.
The dispatcher knows the semantics for instructions, but not the low-level operators (arithmetic, memory I/O, etc), nor the domain (concrete, symbolic, etc) on which those operators operate. These other things are supplied by the argument, which also points to the states that are modified by executing the instructions.
The default implementation returns a null pointer, signifying that instruction semantics are not known.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ bytesPerInstruction()
|
pure virtual |
Valid sizes for encoded machine instructions.
Returns the range of valid sizes for encoded machine instructions. For instance, an x86 instruction can be from one to 15 bytes in length, but a PowerPC PPC32 instruction is always exactly 4 bytes.
Implemented in Rose::BinaryAnalysis::Architecture::Amd64, Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ instructionAlignment()
|
pure virtual |
Alignment for encoded machine instructions.
Implemented in Rose::BinaryAnalysis::Architecture::Amd64, Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ instructionsCanOverlap()
| bool Rose::BinaryAnalysis::Architecture::Base::instructionsCanOverlap | ( | ) | const |
Whether instructions can overlap in memory.
Instructions cannot overlap if the alignment is greater than or equal to the maximum instruction size. Otherwise there is potential for instructions to overlap with one another in memory.
◆ toString() [1/2]
|
virtual |
Unparse an instruction to a string.
The returned string is a simple, one-line string with no leading or trailing white space and no line termination. If the instruction is null, then the word "null" is returned.
Thread safety: Thread safe.
◆ toStringNoAddr()
|
virtual |
Unparse an instruction to a string.
The returned string is a simple, one-line string with no leading or trailing white space and no line termination. If the instruction is null, then the word "null" is returned.
Thread safety: Thread safe.
◆ toString() [2/2]
|
virtual |
Unparse an expression to a string.
The returned string is a simple, one-line string with no leading or trailing white space and no line termination. If the expression is null, then the word "null" is returned.
Thread safety: Thread safe.
◆ instructionMnemonic()
|
pure virtual |
Mnemonic for an instruction.
Returns the mnemonic for a particular instruction.
Thread safety: Thread safe.
Implemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ instructionDescription()
|
virtual |
Description for an instruction.
Returns the description for a particular instruction. The description must be a single line with no leading or trailing white space, no line termination characters, and no non-printable characters. Most subclasses will just return a string based on the instruction mnemonic, such as "push a value onto the stack" for a PUSH instruction. The instruction argument must not be a null pointer and must be valid for this architecture.
The default implementation returns an empty string.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, and Rose::BinaryAnalysis::Architecture::Powerpc.
◆ isUnknown()
|
pure virtual |
Returns true if the instruction is the special "unknown" instruction.
Each instruction architecture in ROSE defines an "unknown" instruction to be used when the disassembler is unable to create a real instruction. This can happen, for instance, if the bit pattern does not represent a valid instruction for the architecture. The instruction must not be a null pointer, and must be valid for this architecture.
Thread safety: Thread safe.
Implemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ isControlTransfer()
|
virtual |
Returns true if the specified instruction is a control transfer instruction.
A control transfer instruction (CTI) is an instruction that alters the normal sequential flow of execution in a program by changing the value of the Program Counter (PC). Examples are branch and jump instructions.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Mips32.
◆ terminatesBasicBlock()
|
pure virtual |
Determines whether the specified instruction normally terminates a basic block.
The analysis generally only looks at the individual instruction and therefore is not very sophisticated. For instance, a conditional branch will always terminate a basic block by this method even if its condition is opaque. The instruction argument must not be a null pointer and must be valid for this architecture.
Thread safety: Thread safe.
Implemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ isFunctionCallFast()
|
virtual |
Returns true if the specified basic block looks like a function call.
If the basic block looks like a function call then this method returns true. If (and only if) the target address is known (i.e., the address of the called function) then target is set to this address (otherwise target is unmodified). If the return address is known or can be guessed, then return_va is initialized to the return address, which is normally the fall-through address of the last instruction; otherwise the return_va is unmodified.
The "fast" and "slow" versions differ only in what kind of anlysis they do. The "fast" version typically looks only at instruction patterns while the slow version might incur more expense by looking at instruction semantics.
The base implementation of the fast method always returns false. The base implementation of the slow method just calls the fast method.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ isFunctionCallSlow()
|
virtual |
Returns true if the specified basic block looks like a function call.
If the basic block looks like a function call then this method returns true. If (and only if) the target address is known (i.e., the address of the called function) then target is set to this address (otherwise target is unmodified). If the return address is known or can be guessed, then return_va is initialized to the return address, which is normally the fall-through address of the last instruction; otherwise the return_va is unmodified.
The "fast" and "slow" versions differ only in what kind of anlysis they do. The "fast" version typically looks only at instruction patterns while the slow version might incur more expense by looking at instruction semantics.
The base implementation of the fast method always returns false. The base implementation of the slow method just calls the fast method.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Motorola, and Rose::BinaryAnalysis::Architecture::X86.
◆ isFunctionReturnFast()
|
virtual |
Returns true if the specified basic block looks like a function return.
The "fast" and "slow" versions differ only in what kind of anlysis they do. The "fast" version typically looks only at instruction patterns while the slow version might incur more expense by looking at instruction semantics.
The base implementaiton of the fast method always returns false. The base implementation of the slow method just calls the fast method.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ isFunctionReturnSlow()
|
virtual |
Returns true if the specified basic block looks like a function return.
The "fast" and "slow" versions differ only in what kind of anlysis they do. The "fast" version typically looks only at instruction patterns while the slow version might incur more expense by looking at instruction semantics.
The base implementaiton of the fast method always returns false. The base implementation of the slow method just calls the fast method.
Thread safety: Thread safe.
◆ branchTarget()
|
virtual |
Obtains the virtual address for a branching instruction.
Returns the branch target address if the specified instruction is a branching instruction and the target is known; otherwise returns nothing.
The default implementation returns nothing.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, and Rose::BinaryAnalysis::Architecture::X86.
◆ getSuccessors() [1/3]
|
virtual |
Control flow successors for a single instruction.
The return value does not consider neighboring instructions, and therefore is quite naive. It returns only the information it can glean from this single instruction. If the returned set of virtual instructions is fully known then the complete argument will be set to true, otherwise false. The instruction must not be null, and must be valid for this architecture.
The default implementation always returns an empty set and clears complete.
Thread safety: Thread saafe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Cil, Rose::BinaryAnalysis::Architecture::Jvm, Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ getSuccessors() [2/3]
| AddressSet Rose::BinaryAnalysis::Architecture::Base::getSuccessors | ( | const std::vector< SgAsmInstruction * > & | basicBlock, |
| bool & | complete | ||
| ) | const |
Control flow successors for a basic block.
The basicBlock argument is a vector of instructions that is assumed to be a basic block that is entered only at the first instruction and exits only at the last instruction. A memory map can supply initial values for the analysis' memory state. The return value is a set of control flow successor virtual addresses, and the complete argument return value indicates whether the returned set is known to be complete (aside from interrupts, faults, etc).
The default implementation calls the single-instruction version, so architecture-specific subclasses might want to override this to do something more sophisticated. However, if the basic block is empty then this function instead returns an empty set and sets complete to true.
Thread safety: Thread safe.
◆ getSuccessors() [3/3]
|
virtual |
Control flow successors for a basic block.
The basicBlock argument is a vector of instructions that is assumed to be a basic block that is entered only at the first instruction and exits only at the last instruction. A memory map can supply initial values for the analysis' memory state. The return value is a set of control flow successor virtual addresses, and the complete argument return value indicates whether the returned set is known to be complete (aside from interrupts, faults, etc).
The default implementation calls the single-instruction version, so architecture-specific subclasses might want to override this to do something more sophisticated. However, if the basic block is empty then this function instead returns an empty set and sets complete to true.
Thread safety: Thread safe.
Reimplemented in Rose::BinaryAnalysis::Architecture::Motorola, and Rose::BinaryAnalysis::Architecture::X86.
◆ functionPrologueMatchers()
|
virtual |
Instruction patterns matching function prologues.
Returns a list of matchers that match sequences of instructions that are often generated by compilers as part of instruction prologues.
The default implementation returns an empty list.
Reimplemented in Rose::BinaryAnalysis::Architecture::Mips32, Rose::BinaryAnalysis::Architecture::Motorola, Rose::BinaryAnalysis::Architecture::Powerpc, and Rose::BinaryAnalysis::Architecture::X86.
◆ basicBlockCreationHooks()
|
virtual |
Architecture-specific basic block callbacks for partitioning.
Returns a list of basic block callbacks used by the partitioner during disassembly.
The default implementation returns an empty list.
Reimplemented in Rose::BinaryAnalysis::Architecture::Motorola, and Rose::BinaryAnalysis::Architecture::X86.
Member Data Documentation
◆ registerDictionary_
|
protected |
Definition at line 37 of file Architecture/Base.h.
◆ interruptDictionary_
|
protected |
Definition at line 38 of file Architecture/Base.h.
◆ callingConventions_
|
protected |
Definition at line 39 of file Architecture/Base.h.
◆ insnToString_
|
protected |
Definition at line 40 of file Architecture/Base.h.
◆ insnToStringNoAddr_
|
protected |
Definition at line 40 of file Architecture/Base.h.
The documentation for this class was generated from the following file:
