2 #ifndef ROSE_BinaryAnalysis_Disassembler_X86_H
3 #define ROSE_BinaryAnalysis_Disassembler_X86_H
4 #include <featureTests.h>
5 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
6 #include <Rose/BinaryAnalysis/Disassembler/Base.h>
8 #include <Rose/BinaryAnalysis/InstructionEnumsX86.h>
9 #include "Cxx_GrammarSerialization.h"
11 #include <boost/serialization/access.hpp>
12 #include <boost/serialization/base_object.hpp>
13 #include <boost/serialization/export.hpp>
14 #include <boost/serialization/split_member.hpp>
17 namespace BinaryAnalysis {
18 namespace Disassembler {
35 SgUnsignedCharList insnbuf;
41 bool branchPredictionEnabled;
42 bool rexPresent, rexW, rexR, rexX, rexB;
44 bool operandSizeOverride;
45 bool addressSizeOverride;
55 bool isUnconditionalJump;
58 : ip(0), insnbufat(0), segOverride(x86_segreg_none), branchPrediction(x86_branch_prediction_none),
59 branchPredictionEnabled(
false), rexPresent(
false), rexW(
false), rexR(
false), rexX(
false), rexB(
false),
60 sizeMustBe64Bit(
false), operandSizeOverride(
false), addressSizeOverride(
false), lock(
false),
61 repeatPrefix(
x86_repeat_none), modregrmByteSet(
false), modregrmByte(0), modeField(0), regField(0),
62 rmField(0), modrm(
nullptr), reg(
nullptr), isUnconditionalJump(
false) {}
68 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
70 friend class boost::serialization::access;
73 void serialize_common(S &s,
const unsigned ) {
77 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(
Base);
78 s & BOOST_SERIALIZATION_NVP(wordSize);
82 void save(S &s,
const unsigned version)
const {
83 serialize_common(s, version);
87 void load(S &s,
const unsigned version) {
88 serialize_common(s, version);
92 BOOST_SERIALIZATION_SPLIT_MEMBER();
103 explicit X86(
size_t wordsize);
111 virtual Base::Ptr
clone()
const override;
119 virtual Unparser::BasePtr
unparser()
const override;
122 AddressSet *successors=
nullptr)
override;
135 class ExceptionX86:
public Exception {
137 ExceptionX86(
const std::string &mesg,
const State &state)
139 ASSERT_require(state.insnbufat <= state.insnbuf.size());
140 if (state.insnbufat > 0)
141 bytes = SgUnsignedCharList(&state.insnbuf[0], &state.insnbuf[0] + state.insnbufat);
142 bit = 8 * state.insnbufat;
145 ExceptionX86(
const std::string &mesg,
const State &state,
size_t bit)
147 ASSERT_require(state.insnbufat <= state.insnbuf.size());
148 if (state.insnbufat > 0)
149 bytes = SgUnsignedCharList(&state.insnbuf[0], &state.insnbuf[0] + state.insnbufat);
156 rmLegacyByte, rmRexByte, rmWord, rmDWord, rmQWord, rmSegment, rmST, rmMM, rmXMM, rmControl, rmDebug, rmReturnNull
161 mmNone, mmF3, mm66, mmF2
173 uint8_t getByte(State &state)
const;
178 uint16_t getWord(State &state)
const;
183 uint32_t getDWord(State &state)
const;
188 uint64_t getQWord(State &state)
const;
204 RegisterMode effectiveOperandMode(State &state)
const {
205 return sizeToMode(effectiveOperandSize(state));
214 SgAsmType *effectiveOperandType(State &state)
const {
215 return sizeToType(effectiveOperandSize(state));
219 bool longMode()
const {
224 MMPrefix mmPrefix(State &state)
const;
227 void not64(State &state)
const {
229 throw ExceptionX86(
"not valid for 64-bit code", state);
234 void setRex(State &state, uint8_t prefix)
const;
252 SgAsmExpression *makeAddrSizeValue(State &state, int64_t val,
size_t bit_offset,
size_t bit_size)
const;
278 return makeRegister(state, fullRegisterNumber, effectiveOperandMode(state));
283 return makeRegister(state, registerNumber + (rexExtension ? 8 : 0), effectiveOperandMode(state));
309 void getModRegRM(State &state, RegisterMode regMode, RegisterMode rmMode,
SgAsmType *t,
SgAsmType *tForReg =
nullptr)
const;
316 void fillInModRM(State &state, RegisterMode rmMode,
SgAsmType *t)
const;
326 void requireMemory(State &state)
const {
327 if (!state.modregrmByteSet)
328 throw ExceptionX86(
"requires Mod/RM byte", state);
329 if (state.modeField == 3)
330 throw ExceptionX86(
"requires memory", state);
440 void init(
size_t wordsize);
442 #if 0 // is this ever used?
449 state.branchPredictionEnabled = state.branchPrediction != x86_branch_prediction_none;
455 void startInstruction(State &state, rose_addr_t start_va,
const uint8_t *buf,
size_t bufsz)
const {
457 state.insnbuf = SgUnsignedCharList(buf, buf+bufsz);
461 state.segOverride = x86_segreg_none;
462 state.branchPrediction = x86_branch_prediction_none;
463 state.branchPredictionEnabled =
false;
464 state.rexPresent = state.rexW = state.rexR = state.rexX = state.rexB =
false;
465 state.sizeMustBe64Bit =
false;
466 state.operandSizeOverride =
false;
467 state.addressSizeOverride =
false;
470 state.modregrmByteSet =
false;
471 state.modregrmByte = state.modeField = state.regField = state.rmField = 0;
472 state.modrm = state.reg =
nullptr;
473 state.isUnconditionalJump =
false;
485 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
X86Ptr Ptr
Reference counting pointer.
Instruction is for a 64-bit architecture.
static Ptr instance(size_t wordSize)
Allocating constructor.
Base class for references to a machine register.
virtual Base::Ptr clone() const override
Creates a new copy of a disassembler.
virtual bool canDisassemble(SgAsmGenericHeader *) const override
Predicate determining the suitability of a disassembler for a specific file header.
rose_addr_t ip
Virtual address where failure occurred; zero if no associated instruction.
virtual SgAsmInstruction * makeUnknownInstruction(const Exception &) override
Makes an unknown instruction from an exception.
Base class for machine instructions.
X86BranchPrediction
Intel x86 branch prediction types.
size_t bit
Bit offset in instruction byte sequence where disassembly failed (bit/8 is the index into the "bytes"...
Rose::BinaryAnalysis::X86BranchPrediction const & get_branchPrediction() const
Property: An enum constant describing branch prediction.
rose_addr_t const & get_address() const
Property: Starting virtual address.
bool const & get_lockPrefix() const
Property: Whether the x86 lock prefix was present.
Rose::BinaryAnalysis::X86SegmentRegister const & get_segmentOverride() const
Property: The segment override register.
Main namespace for the ROSE library.
Rose::BinaryAnalysis::X86InstructionSize const & get_baseSize() const
Property: An enum constant describing the base size of an x86 instruction.
MemoryMapPtr Ptr
Reference counting pointer.
Sawyer::SharedPointer< X86 > X86Ptr
Reference counted pointer for Intel X86 decoder.
Reference to memory locations.
Exception(const std::string &reason)
A bare exception not bound to any particular instruction.
Disassembler for the x86 architecture.
virtual Unparser::BasePtr unparser() const override
Unparser.
Represents one Intel x86 machine instruction.
Base class for expressions.
Base class for binary types.
X86SegmentRegister
Intel x86 segment registers.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &map, rose_addr_t va, AddressSet *successors=nullptr) override
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
SgUnsignedCharList bytes
Bytes (partial) of failed disassembly, including byte at failure.
X86InstructionKind
List of all x86 instructions known to the ROSE disassembler/assembler.
X86InstructionSize
Intel x86 instruction size constants.
Virtual base class for instruction disassemblers.
X86RepeatPrefix
Intel x86 instruction repeat prefix.