Description
Architecture-specific information for MIPS with 32-bit word size.
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MIPS (Microprocessor without Interlocked Pipelined Stages)[1] is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies, based in the United States.
There are multiple versions of MIPS: including MIPS I, II, III, IV, and V; as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.
The MIPS architecture has several optional extensions. MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX (MaDMaX) which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room, and MIPS MT, which adds multithreading capability.
#include <Rose/BinaryAnalysis/Architecture/Mips32.h>
Public Types | |
| using | Ptr = Mips32Ptr |
 Public Types inherited from Rose::BinaryAnalysis::Architecture::Base | |
| using | Ptr = BasePtr |
| Reference counting pointer. | |
| using | ConstPtr = BaseConstPtr |
| Reference counting pointer to const object. | |
Public Member Functions | |
| RegisterDictionaryPtr | registerDictionary () const override |
| Property: Register dictionary. | |
| RegisterDictionaryPtr | interruptDictionary () const override |
| Property: Interrupt dictionary. | |
| bool | matchesHeader (SgAsmGenericHeader *) const override |
| Tests whether this architecture matches a file header. | |
| Sawyer::Container::Interval< size_t > | bytesPerInstruction () const override |
| Valid sizes for encoded machine instructions. | |
| Alignment | instructionAlignment () const override |
| Alignment for encoded machine instructions. | |
| std::string | instructionMnemonic (const SgAsmInstruction *) const override |
| Mnemonic for an instruction. | |
| std::string | instructionDescription (const SgAsmInstruction *) const override |
| Description for an instruction. | |
| bool | isUnknown (const SgAsmInstruction *) const override |
| Returns true if the instruction is the special "unknown" instruction. | |
| bool | isControlTransfer (const SgAsmInstruction *) const override |
| Returns true if the specified instruction is a control transfer instruction. | |
| bool | terminatesBasicBlock (SgAsmInstruction *) const override |
| Determines whether the specified instruction normally terminates a basic block. | |
| bool | isFunctionCallFast (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override |
| Returns true if the specified basic block looks like a function call. | |
| bool | isFunctionReturnFast (const std::vector< SgAsmInstruction * > &) const override |
| Returns true if the specified basic block looks like a function return. | |
| Sawyer::Optional< rose_addr_t > | branchTarget (SgAsmInstruction *) const override |
| Obtains the virtual address for a branching instruction. | |
| AddressSet | getSuccessors (SgAsmInstruction *, bool &complete) const override |
| Control flow successors for a single instruction. | |
| Disassembler::BasePtr | newInstructionDecoder () const override |
| Construct and return a new instruction decoder. | |
| Unparser::BasePtr | newUnparser () const override |
| Construct and return a new instruction unparser. | |
| InstructionSemantics::BaseSemantics::DispatcherPtr | newInstructionDispatcher (const InstructionSemantics::BaseSemantics::RiscOperatorsPtr &) const override |
| Construct and return a new instruction dispatcher. | |
| std::vector< Partitioner2::FunctionPrologueMatcherPtr > | functionPrologueMatchers (const Partitioner2::EnginePtr &) const override |
| Instruction patterns matching function prologues. | |
| Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base | |
| const std::string & | name () const |
| Property: Architecture definition name. | |
| ByteOrder::Endianness | byteOrder () const |
| Property: Byte order for memory. | |
| virtual const CallingConvention::Dictionary & | callingConventions () const |
| Property: Calling convention definitions. | |
| virtual bool | matchesName (const std::string &) const |
| Tests whether this architecture matches a name. | |
| bool | instructionsCanOverlap () const |
| Whether instructions can overlap in memory. | |
| virtual std::string | toString (const SgAsmExpression *) const |
| Unparse an expression to a string. | |
| virtual std::vector< Partitioner2::BasicBlockCallbackPtr > | basicBlockCreationHooks (const Partitioner2::EnginePtr &) const |
| Architecture-specific basic block callbacks for partitioning. | |
| const Sawyer::Optional< size_t > & | registrationId () const |
| Property: Registration identification number. | |
| void | registrationId (const Sawyer::Optional< size_t > &) |
| Property: Registration identification number. | |
| size_t | bytesPerWord () const |
| Property: Word size. | |
| size_t | bitsPerWord () const |
| Property: Word size. | |
| virtual Unparser::BasePtr | newInstructionUnparser () const |
| Construct and return a new instruction unparser. | |
| virtual std::string | toString (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual std::string | toStringNoAddr (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual bool | isFunctionCallSlow (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const |
| Returns true if the specified basic block looks like a function call. | |
| virtual bool | isFunctionReturnSlow (const std::vector< SgAsmInstruction * > &) const |
| Returns true if the specified basic block looks like a function return. | |
| AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete) const |
| Control flow successors for a basic block. | |
| virtual AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete, const MemoryMapPtr &initial_memory) const |
| Control flow successors for a basic block. | |
Static Public Member Functions | |
| static Ptr | instance (ByteOrder::Endianness) |
| Allocating constructor. | |
Protected Member Functions | |
| Mips32 (ByteOrder::Endianness) | |
| Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base | |
| Base (const std::string &name, size_t bytesPerWord, ByteOrder::Endianness byteOrder) | |
| Ptr | ptr () |
| ConstPtr | constPtr () const |
| virtual Unparser::BasePtr | insnUnparser () const |
Additional Inherited Members | |
| Protected Attributes inherited from Rose::BinaryAnalysis::Architecture::Base | |
| Sawyer::Cached< RegisterDictionaryPtr > | registerDictionary_ |
| Sawyer::Cached< RegisterDictionaryPtr > | interruptDictionary_ |
| Sawyer::Cached< CallingConvention::Dictionary > | callingConventions_ |
| Sawyer::Cached< Unparser::Base::Ptr > | insnToString_ |
| Sawyer::Cached< Unparser::Base::Ptr > | insnToStringNoAddr_ |
Member Typedef Documentation
◆ Ptr
| using Rose::BinaryAnalysis::Architecture::Mips32::Ptr = Mips32Ptr |
Member Function Documentation
◆ registerDictionary()
|
overridevirtual |
Property: Register dictionary.
The register dictionary defines a mapping between register names and register descriptors (RegisterDescriptor), and thus how the registers map into hardware.
Since dictionaries are generally not modified, it is permissible for this function to return the same dictionary every time it's called. The dictionary can be constructed on the first call.
Thread safety: Thread safe.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ interruptDictionary()
|
overridevirtual |
Property: Interrupt dictionary.
The interrupt dictionary (a kind of register dictionary) defines a mapping between interrupt names and descriptors (RegisterDescriptor), and thus how the interrupt names map to hardware. Interrupts are normally single-bit values that indicate whether the interrupt is in a raised or cleared state. Interrupts in ROSE have a major and minor number since they use the same addressing mechanism as registers.
Since dictionaries are generally not modified, it is permissible for this funtion to return the same dictionary every time it's called. The dictionary can be constructed on the first call.
Thread safety: Thread safe.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ matchesHeader()
|
overridevirtual |
Tests whether this architecture matches a file header.
Returns true if this architecture matches the specified file header, and false otherwise.
The default implementation always returns false.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ bytesPerInstruction()
|
overridevirtual |
Valid sizes for encoded machine instructions.
Returns the range of valid sizes for encoded machine instructions. For instance, an x86 instruction can be from one to 15 bytes in length, but a PowerPC PPC32 instruction is always exactly 4 bytes.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ instructionAlignment()
|
overridevirtual |
Alignment for encoded machine instructions.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ instructionMnemonic()
|
overridevirtual |
Mnemonic for an instruction.
Returns the mnemonic for a particular instruction.
Thread safety: Thread safe.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ instructionDescription()
|
overridevirtual |
Description for an instruction.
Returns the description for a particular instruction. The description must be a single line with no leading or trailing white space, no line termination characters, and no non-printable characters. Most subclasses will just return a string based on the instruction mnemonic, such as "push a value onto the stack" for a PUSH instruction. The instruction argument must not be a null pointer and must be valid for this architecture.
The default implementation returns an empty string.
Thread safety: Thread safe.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ isUnknown()
|
overridevirtual |
Returns true if the instruction is the special "unknown" instruction.
Each instruction architecture in ROSE defines an "unknown" instruction to be used when the disassembler is unable to create a real instruction. This can happen, for instance, if the bit pattern does not represent a valid instruction for the architecture. The instruction must not be a null pointer, and must be valid for this architecture.
Thread safety: Thread safe.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ isControlTransfer()
|
overridevirtual |
Returns true if the specified instruction is a control transfer instruction.
A control transfer instruction (CTI) is an instruction that alters the normal sequential flow of execution in a program by changing the value of the Program Counter (PC). Examples are branch and jump instructions.
Thread safety: Thread safe.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ terminatesBasicBlock()
|
overridevirtual |
Determines whether the specified instruction normally terminates a basic block.
The analysis generally only looks at the individual instruction and therefore is not very sophisticated. For instance, a conditional branch will always terminate a basic block by this method even if its condition is opaque. The instruction argument must not be a null pointer and must be valid for this architecture.
Thread safety: Thread safe.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ isFunctionCallFast()
|
overridevirtual |
Returns true if the specified basic block looks like a function call.
If the basic block looks like a function call then this method returns true. If (and only if) the target address is known (i.e., the address of the called function) then target is set to this address (otherwise target is unmodified). If the return address is known or can be guessed, then return_va is initialized to the return address, which is normally the fall-through address of the last instruction; otherwise the return_va is unmodified.
The "fast" and "slow" versions differ only in what kind of anlysis they do. The "fast" version typically looks only at instruction patterns while the slow version might incur more expense by looking at instruction semantics.
The base implementation of the fast method always returns false. The base implementation of the slow method just calls the fast method.
Thread safety: Thread safe.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ isFunctionReturnFast()
|
overridevirtual |
Returns true if the specified basic block looks like a function return.
The "fast" and "slow" versions differ only in what kind of anlysis they do. The "fast" version typically looks only at instruction patterns while the slow version might incur more expense by looking at instruction semantics.
The base implementaiton of the fast method always returns false. The base implementation of the slow method just calls the fast method.
Thread safety: Thread safe.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ branchTarget()
|
overridevirtual |
Obtains the virtual address for a branching instruction.
Returns the branch target address if the specified instruction is a branching instruction and the target is known; otherwise returns nothing.
The default implementation returns nothing.
Thread safety: Thread safe.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ getSuccessors()
|
overridevirtual |
Control flow successors for a single instruction.
The return value does not consider neighboring instructions, and therefore is quite naive. It returns only the information it can glean from this single instruction. If the returned set of virtual instructions is fully known then the complete argument will be set to true, otherwise false. The instruction must not be null, and must be valid for this architecture.
The default implementation always returns an empty set and clears complete.
Thread safety: Thread saafe.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ newInstructionDecoder()
|
overridevirtual |
Construct and return a new instruction decoder.
Returns a new decoder for this architecture if possible, otherwise a null pointer.
Thread safety: Thread safe.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ newUnparser()
|
overridevirtual |
Construct and return a new instruction unparser.
An unparser is responsible for generating pseudo assembly listings.
The newUnparser returns a default configured unparser suitable for unparsing instructions in the context of an assembly listing. The newInstructionUnparser returns a parser configured to show individual instructions showing only the instruction address, the instruction mnemonic, and the operands.
Example: The default instruction unparser uses color by default. If you want to turn off the color, you must create a new unparser, configure it to disable color, and then use it to unparse the instruction.
Thread safety: Thread safe.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ newInstructionDispatcher()
|
overridevirtual |
Construct and return a new instruction dispatcher.
The dispatcher knows the semantics for instructions, but not the low-level operators (arithmetic, memory I/O, etc), nor the domain (concrete, symbolic, etc) on which those operators operate. These other things are supplied by the argument, which also points to the states that are modified by executing the instructions.
The default implementation returns a null pointer, signifying that instruction semantics are not known.
Thread safety: Thread safe.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ functionPrologueMatchers()
|
overridevirtual |
Instruction patterns matching function prologues.
Returns a list of matchers that match sequences of instructions that are often generated by compilers as part of instruction prologues.
The default implementation returns an empty list.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
The documentation for this class was generated from the following file:
