1#ifndef ROSE_BinaryAnalysis_Architecture_Mips32_H 
    2#define ROSE_BinaryAnalysis_Architecture_Mips32_H 
    3#include <featureTests.h> 
    4#ifdef ROSE_ENABLE_BINARY_ANALYSIS 
    5#include <Rose/BinaryAnalysis/Architecture/Base.h> 
    8namespace BinaryAnalysis {
 
   61    std::vector<Partitioner2::FunctionPrologueMatcherPtr>
 
 
Information about alignments.
 
Base class for architecture definitions.
 
Architecture-specific information for MIPS with 32-bit word size.
 
RegisterDictionaryPtr interruptDictionary() const override
Property: Interrupt dictionary.
 
bool isControlTransfer(const SgAsmInstruction *) const override
Returns true if the specified instruction is a control transfer instruction.
 
bool isUnknown(const SgAsmInstruction *) const override
Returns true if the instruction is the special "unknown" instruction.
 
RegisterDictionaryPtr registerDictionary() const override
Property: Register dictionary.
 
Sawyer::Container::Interval< size_t > bytesPerInstruction() const override
Valid sizes for encoded machine instructions.
 
bool isFunctionCallFast(const std::vector< SgAsmInstruction * > &, Address *target, Address *ret) const override
Returns true if the specified basic block looks like a function call.
 
Alignment instructionAlignment() const override
Alignment for encoded machine instructions.
 
bool terminatesBasicBlock(SgAsmInstruction *) const override
Determines whether the specified instruction normally terminates a basic block.
 
Unparser::BasePtr newUnparser() const override
Construct and return a new instruction unparser.
 
static Ptr instance(ByteOrder::Endianness)
Allocating constructor.
 
InstructionSemantics::BaseSemantics::DispatcherPtr newInstructionDispatcher(const InstructionSemantics::BaseSemantics::RiscOperatorsPtr &) const override
Construct and return a new instruction dispatcher.
 
std::vector< Partitioner2::FunctionPrologueMatcherPtr > functionPrologueMatchers(const Partitioner2::EnginePtr &) const override
Instruction patterns matching function prologues.
 
Sawyer::Optional< Address > branchTarget(SgAsmInstruction *) const override
Obtains the virtual address for a branching instruction.
 
AddressSet getSuccessors(SgAsmInstruction *, bool &complete) const override
Control flow successors for a single instruction.
 
Disassembler::BasePtr newInstructionDecoder() const override
Construct and return a new instruction decoder.
 
bool isFunctionReturnFast(const std::vector< SgAsmInstruction * > &) const override
Returns true if the specified basic block looks like a function return.
 
std::string instructionDescription(const SgAsmInstruction *) const override
Description for an instruction.
 
std::string instructionMnemonic(const SgAsmInstruction *) const override
Mnemonic for an instruction.
 
bool matchesHeader(SgAsmGenericHeader *) const override
Tests whether this architecture matches a file header.
 
Range of values delimited by endpoints.
 
Holds a value or nothing.
 
Base class for machine instructions.
 
std::shared_ptr< Mips32 > Mips32Ptr
Reference counted pointer for Mips32.
 
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
 
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
 
std::uint64_t Address
Address.
 
const char * Architecture(int64_t)
Convert Rose::BinaryAnalysis::Disassembler::Mips::Decoder::Architecture enum constant to a string.