Disassembler/Mips.h

/* Disassembly specific to the MIPS architecture */
#ifndef ROSE_BinaryAnalysis_Disassembler_Mips_H
#define ROSE_BinaryAnalysis_Disassembler_Mips_H
#include <featureTests.h>
#ifdef ROSE_ENABLE_BINARY_ANALYSIS
#include <Rose/BinaryAnalysis/Disassembler/Base.h>

#include <Rose/BinaryAnalysis/ByteOrder.h>
#include <Rose/BinaryAnalysis/InstructionEnumsMips.h>

#include <SageBuilderAsm.h>

namespace Rose {
namespace BinaryAnalysis {
namespace Disassembler {

class Mips: public Base {
public:
    using Ptr = MipsPtr;

protected:
    explicit Mips(ByteOrder::Endianness sex = ByteOrder::ORDER_MSB);

public:
    static Ptr instance(ByteOrder::Endianness sex = ByteOrder::ORDER_MSB);

    virtual Base::Ptr clone() const override;
    virtual bool canDisassemble(SgAsmGenericHeader*) const override;
    virtual SgAsmInstruction *disassembleOne(const MemoryMap::Ptr&, rose_addr_t start_va,
                                             AddressSet *successors=NULL) override;
    virtual SgAsmInstruction *makeUnknownInstruction(const Exception&) override;
    SgAsmMipsInstruction *makeUnknownInstruction(rose_addr_t insn_va, unsigned opcode) const;
    virtual Unparser::BasePtr unparser() const override;

    class Decoder {
    public:
        enum Architecture { Release1, Release2, Release3, Micro };
        Decoder(Architecture arch, unsigned match, unsigned mask): arch(arch), match(match), mask(mask) {}
        virtual ~Decoder() {}
        Architecture arch;      // architecture where this instruction was introduced
        unsigned match;         // value of compared bits
        unsigned mask;          // bits of 'match' that will be compared
        typedef Mips D;
        virtual SgAsmMipsInstruction *operator()(rose_addr_t insn_va, const D *d, unsigned insn_bits) = 0;
    };

    Decoder *find_idis(rose_addr_t insn_va, unsigned insn_bits) const;

    void insert_idis(Decoder*, bool replace=false);

    SgAsmMipsInstruction *disassemble_insn(rose_addr_t insn_va, unsigned insn_bits) const;


    // The following functions are used by the various instruction-specific Mips32 subclasses.

    SgAsmMipsInstruction *makeInstruction(rose_addr_t insn_va, MipsInstructionKind, const std::string &mnemonic,
                                          SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL,
                                          SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL) const;

    SgAsmRegisterReferenceExpression *makeRegister(rose_addr_t insn_va, unsigned regnum) const;

    SgAsmRegisterReferenceExpression *makeFpRegister(rose_addr_t insn_va, unsigned regnum) const;

    SgAsmRegisterReferenceExpression *makeCp0Register(rose_addr_t insn_va, unsigned regnum, unsigned sel) const;

    SgAsmRegisterReferenceExpression *makeCp2Register(unsigned regnum) const;

    SgAsmRegisterReferenceExpression *makeFpccRegister(rose_addr_t insn_va, unsigned cc) const;

    SgAsmRegisterReferenceExpression *makeCp2ccRegister(unsigned cc) const;

    SgAsmRegisterReferenceExpression *makeHwRegister(unsigned regnum) const;

    SgAsmRegisterReferenceExpression *makeShadowRegister(rose_addr_t insn_va, unsigned regnum) const;

    SgAsmIntegerValueExpression *makeImmediate8(unsigned value, size_t bit_offset, size_t nbits) const;

    SgAsmIntegerValueExpression *makeImmediate16(unsigned value, size_t bit_offset, size_t nbits) const;

    SgAsmIntegerValueExpression *makeImmediate32(unsigned value, size_t bit_offset, size_t nbits) const;

    SgAsmIntegerValueExpression *makeBranchTargetRelative(rose_addr_t insn_va, unsigned offset16, size_t bit_offset,
                                                          size_t nbits) const;

    SgAsmIntegerValueExpression *makeBranchTargetAbsolute(rose_addr_t insn_va, unsigned insn_index, size_t bit_offset,
                                                          size_t nbits) const;

    SgAsmBinaryAdd *makeRegisterOffset(rose_addr_t insn_va, unsigned gprnum, unsigned offset16) const;

    SgAsmBinaryAdd *makeRegisterIndexed(rose_addr_t insn_va, unsigned base_gprnum, unsigned index_gprnum) const;

    SgAsmMemoryReferenceExpression *makeMemoryReference(SgAsmExpression *addr, SgAsmType *type) const;


protected:
    void init(ByteOrder::Endianness);

protected:
    std::vector<Decoder*> idis_table;
};

} // namespace
} // namespace
} // namespace

#endif
#endif