ROSE  0.11.98.0
Disassembler/Mips.h
1 /* Disassembly specific to the MIPS architecture */
2 #ifndef ROSE_BinaryAnalysis_Disassembler_Mips_H
3 #define ROSE_BinaryAnalysis_Disassembler_Mips_H
4 #include <featureTests.h>
5 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
6 #include <Rose/BinaryAnalysis/Disassembler/Base.h>
7 
8 #include <Rose/BinaryAnalysis/InstructionEnumsMips.h>
9 
10 #include <ByteOrder.h>
11 #include <SageBuilderAsm.h>
12 
13 namespace Rose {
14 namespace BinaryAnalysis {
15 namespace Disassembler {
16 
17 class Mips: public Base {
18 public:
20  using Ptr = MipsPtr;
21 
22 protected:
23  explicit Mips(ByteOrder::Endianness sex = ByteOrder::ORDER_MSB);
24 
25 public:
29  static Ptr instance(ByteOrder::Endianness sex = ByteOrder::ORDER_MSB);
30 
31  virtual Base::Ptr clone() const override;
32  virtual bool canDisassemble(SgAsmGenericHeader*) const override;
33  virtual SgAsmInstruction *disassembleOne(const MemoryMap::Ptr&, rose_addr_t start_va,
34  AddressSet *successors=NULL) override;
35  virtual SgAsmInstruction *makeUnknownInstruction(const Exception&) override;
36  SgAsmMipsInstruction *makeUnknownInstruction(rose_addr_t insn_va, unsigned opcode) const;
37  virtual Unparser::BasePtr unparser() const override;
38 
45  class Decoder {
46  public:
47  enum Architecture { Release1, Release2, Release3, Micro };
48  Decoder(Architecture arch, unsigned match, unsigned mask): arch(arch), match(match), mask(mask) {}
49  virtual ~Decoder() {}
50  Architecture arch; // architecture where this instruction was introduced
51  unsigned match; // value of compared bits
52  unsigned mask; // bits of 'match' that will be compared
53  typedef Mips D;
54  virtual SgAsmMipsInstruction *operator()(rose_addr_t insn_va, const D *d, unsigned insn_bits) = 0;
55  };
56 
60  Decoder *find_idis(rose_addr_t insn_va, unsigned insn_bits) const;
61 
65  void insert_idis(Decoder*, bool replace=false);
66 
71  SgAsmMipsInstruction *disassemble_insn(rose_addr_t insn_va, unsigned insn_bits) const;
72 
73 
75  // The following functions are used by the various instruction-specific Mips32 subclasses.
76 
78  SgAsmMipsInstruction *makeInstruction(rose_addr_t insn_va, MipsInstructionKind, const std::string &mnemonic,
79  SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL,
80  SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL) const;
81 
83  SgAsmRegisterReferenceExpression *makeRegister(rose_addr_t insn_va, unsigned regnum) const;
84 
86  SgAsmRegisterReferenceExpression *makeFpRegister(rose_addr_t insn_va, unsigned regnum) const;
87 
89  SgAsmRegisterReferenceExpression *makeCp0Register(rose_addr_t insn_va, unsigned regnum, unsigned sel) const;
90 
92  SgAsmRegisterReferenceExpression *makeCp2Register(unsigned regnum) const;
93 
97  SgAsmRegisterReferenceExpression *makeFpccRegister(rose_addr_t insn_va, unsigned cc) const;
98 
101 
103  SgAsmRegisterReferenceExpression *makeHwRegister(unsigned regnum) const;
104 
106  SgAsmRegisterReferenceExpression *makeShadowRegister(rose_addr_t insn_va, unsigned regnum) const;
107 
110  SgAsmIntegerValueExpression *makeImmediate8(unsigned value, size_t bit_offset, size_t nbits) const;
111 
114  SgAsmIntegerValueExpression *makeImmediate16(unsigned value, size_t bit_offset, size_t nbits) const;
115 
118  SgAsmIntegerValueExpression *makeImmediate32(unsigned value, size_t bit_offset, size_t nbits) const;
119 
123  SgAsmIntegerValueExpression *makeBranchTargetRelative(rose_addr_t insn_va, unsigned offset16, size_t bit_offset,
124  size_t nbits) const;
125 
129  SgAsmIntegerValueExpression *makeBranchTargetAbsolute(rose_addr_t insn_va, unsigned insn_index, size_t bit_offset,
130  size_t nbits) const;
131 
135  SgAsmBinaryAdd *makeRegisterOffset(rose_addr_t insn_va, unsigned gprnum, unsigned offset16) const;
136 
138  SgAsmBinaryAdd *makeRegisterIndexed(rose_addr_t insn_va, unsigned base_gprnum, unsigned index_gprnum) const;
139 
142 
144 
145 protected:
146  void init(ByteOrder::Endianness);
147 
148 protected:
151  std::vector<Decoder*> idis_table;
152 };
153 
154 } // namespace
155 } // namespace
156 } // namespace
157 
158 #endif
159 #endif
Decoder * find_idis(rose_addr_t insn_va, unsigned insn_bits) const
Find an instruction-specific disassembler.
Expression that adds two operands.
Base class for references to a machine register.
SgAsmBinaryAdd * makeRegisterIndexed(rose_addr_t insn_va, unsigned base_gprnum, unsigned index_gprnum) const
Build a register index expression.
SgAsmRegisterReferenceExpression * makeFpccRegister(rose_addr_t insn_va, unsigned cc) const
Create a new floating point condition flag register reference expression.
Base class for machine instructions.
SgAsmIntegerValueExpression * makeBranchTargetAbsolute(rose_addr_t insn_va, unsigned insn_index, size_t bit_offset, size_t nbits) const
Create a 32-bit branch address from an instruction index value.
SgAsmBinaryAdd * makeRegisterOffset(rose_addr_t insn_va, unsigned gprnum, unsigned offset16) const
Build an expression for an offset from a register.
Main namespace for the ROSE library.
virtual bool canDisassemble(SgAsmGenericHeader *) const override
Predicate determining the suitability of a disassembler for a specific file header.
virtual SgAsmInstruction * makeUnknownInstruction(const Exception &) override
Makes an unknown instruction from an exception.
SgAsmRegisterReferenceExpression * makeCp2Register(unsigned regnum) const
Create a new register reference for Coprocessor 2.
SgAsmMemoryReferenceExpression * makeMemoryReference(SgAsmExpression *addr, SgAsmType *type) const
Build a memory reference expression.
SgAsmMipsInstruction * disassemble_insn(rose_addr_t insn_va, unsigned insn_bits) const
Disassemble a single instruction.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &, rose_addr_t start_va, AddressSet *successors=NULL) override
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
SgAsmRegisterReferenceExpression * makeRegister(rose_addr_t insn_va, unsigned regnum) const
Create a new general purpose register reference expression.
static Ptr instance(ByteOrder::Endianness sex=ByteOrder::ORDER_MSB)
Allocating constructor for MIPS decoder.
Reference to memory locations.
std::vector< Decoder * > idis_table
Table of instruction-specific disassemblers.
void insert_idis(Decoder *, bool replace=false)
Insert an instruction-specific disassembler.
Base class for container file headers.
SgAsmIntegerValueExpression * makeImmediate8(unsigned value, size_t bit_offset, size_t nbits) const
Create a new 8-bit value expression from an 8-bit value.
Base class for integer values.
SgAsmIntegerValueExpression * makeImmediate32(unsigned value, size_t bit_offset, size_t nbits) const
Create a new 32-bit value expression from a 32-bit value.
SgAsmIntegerValueExpression * makeBranchTargetRelative(rose_addr_t insn_va, unsigned offset16, size_t bit_offset, size_t nbits) const
Create a 32-bit PC-relative branch target address from a 16-bit offset.
Interface for disassembling a single instruction.
SgAsmRegisterReferenceExpression * makeShadowRegister(rose_addr_t insn_va, unsigned regnum) const
Create a new register reference for a shadow GPR.
SgAsmRegisterReferenceExpression * makeHwRegister(unsigned regnum) const
Create a new register reference for a hardware register.
Base class for expressions.
Binary analysis.
Represents one MIPS machine instruction.
Base class for binary types.
SgAsmRegisterReferenceExpression * makeCp2ccRegister(unsigned cc) const
Create a new register reference for a COP2 condition code.
virtual Unparser::BasePtr unparser() const override
Unparser.
SgAsmMipsInstruction * makeInstruction(rose_addr_t insn_va, MipsInstructionKind, const std::string &mnemonic, SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL, SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL) const
Create a new instruction.
virtual Base::Ptr clone() const override
Creates a new copy of a disassembler.
Sawyer::SharedPointer< Mips > MipsPtr
Reference counted pointer for Mips decoder.
Virtual base class for instruction disassemblers.
SgAsmIntegerValueExpression * makeImmediate16(unsigned value, size_t bit_offset, size_t nbits) const
Create a new 16-bit value expression from a 16-bit value.
SgAsmRegisterReferenceExpression * makeFpRegister(rose_addr_t insn_va, unsigned regnum) const
Create a new floating point register reference expression.
SgAsmRegisterReferenceExpression * makeCp0Register(rose_addr_t insn_va, unsigned regnum, unsigned sel) const
Create a new register reference for Coprocessor 0.