2 #ifndef ROSE_BinaryAnalysis_Disassembler_Mips_H
3 #define ROSE_BinaryAnalysis_Disassembler_Mips_H
4 #include <featureTests.h>
5 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
6 #include <Rose/BinaryAnalysis/Disassembler/Base.h>
8 #include <Rose/BinaryAnalysis/InstructionEnumsMips.h>
10 #include <ByteOrder.h>
11 #include <SageBuilderAsm.h>
14 namespace BinaryAnalysis {
15 namespace Disassembler {
23 explicit Mips(ByteOrder::Endianness sex = ByteOrder::ORDER_MSB);
29 static Ptr instance(ByteOrder::Endianness sex = ByteOrder::ORDER_MSB);
47 enum Architecture { Release1, Release2, Release3, Micro };
48 Decoder(Architecture arch,
unsigned match,
unsigned mask): arch(arch), match(match), mask(mask) {}
54 virtual SgAsmMipsInstruction *operator()(rose_addr_t insn_va,
const D *d,
unsigned insn_bits) = 0;
146 void init(ByteOrder::Endianness);
Decoder * find_idis(rose_addr_t insn_va, unsigned insn_bits) const
Find an instruction-specific disassembler.
Expression that adds two operands.
Base class for references to a machine register.
SgAsmBinaryAdd * makeRegisterIndexed(rose_addr_t insn_va, unsigned base_gprnum, unsigned index_gprnum) const
Build a register index expression.
SgAsmRegisterReferenceExpression * makeFpccRegister(rose_addr_t insn_va, unsigned cc) const
Create a new floating point condition flag register reference expression.
Base class for machine instructions.
SgAsmIntegerValueExpression * makeBranchTargetAbsolute(rose_addr_t insn_va, unsigned insn_index, size_t bit_offset, size_t nbits) const
Create a 32-bit branch address from an instruction index value.
SgAsmBinaryAdd * makeRegisterOffset(rose_addr_t insn_va, unsigned gprnum, unsigned offset16) const
Build an expression for an offset from a register.
Main namespace for the ROSE library.
virtual bool canDisassemble(SgAsmGenericHeader *) const override
Predicate determining the suitability of a disassembler for a specific file header.
virtual SgAsmInstruction * makeUnknownInstruction(const Exception &) override
Makes an unknown instruction from an exception.
SgAsmRegisterReferenceExpression * makeCp2Register(unsigned regnum) const
Create a new register reference for Coprocessor 2.
SgAsmMemoryReferenceExpression * makeMemoryReference(SgAsmExpression *addr, SgAsmType *type) const
Build a memory reference expression.
SgAsmMipsInstruction * disassemble_insn(rose_addr_t insn_va, unsigned insn_bits) const
Disassemble a single instruction.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &, rose_addr_t start_va, AddressSet *successors=NULL) override
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
SgAsmRegisterReferenceExpression * makeRegister(rose_addr_t insn_va, unsigned regnum) const
Create a new general purpose register reference expression.
static Ptr instance(ByteOrder::Endianness sex=ByteOrder::ORDER_MSB)
Allocating constructor for MIPS decoder.
Reference to memory locations.
std::vector< Decoder * > idis_table
Table of instruction-specific disassemblers.
void insert_idis(Decoder *, bool replace=false)
Insert an instruction-specific disassembler.
SgAsmIntegerValueExpression * makeImmediate8(unsigned value, size_t bit_offset, size_t nbits) const
Create a new 8-bit value expression from an 8-bit value.
Base class for integer values.
SgAsmIntegerValueExpression * makeImmediate32(unsigned value, size_t bit_offset, size_t nbits) const
Create a new 32-bit value expression from a 32-bit value.
SgAsmIntegerValueExpression * makeBranchTargetRelative(rose_addr_t insn_va, unsigned offset16, size_t bit_offset, size_t nbits) const
Create a 32-bit PC-relative branch target address from a 16-bit offset.
Interface for disassembling a single instruction.
SgAsmRegisterReferenceExpression * makeShadowRegister(rose_addr_t insn_va, unsigned regnum) const
Create a new register reference for a shadow GPR.
SgAsmRegisterReferenceExpression * makeHwRegister(unsigned regnum) const
Create a new register reference for a hardware register.
Base class for expressions.
MipsInstructionKind
Kinds of MIPS instructions.
Represents one MIPS machine instruction.
Base class for binary types.
SgAsmRegisterReferenceExpression * makeCp2ccRegister(unsigned cc) const
Create a new register reference for a COP2 condition code.
virtual Unparser::BasePtr unparser() const override
Unparser.
SgAsmMipsInstruction * makeInstruction(rose_addr_t insn_va, MipsInstructionKind, const std::string &mnemonic, SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL, SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL) const
Create a new instruction.
Exception thrown by the disassemblers.
virtual Base::Ptr clone() const override
Creates a new copy of a disassembler.
Sawyer::SharedPointer< Mips > MipsPtr
Reference counted pointer for Mips decoder.
Virtual base class for instruction disassemblers.
SgAsmIntegerValueExpression * makeImmediate16(unsigned value, size_t bit_offset, size_t nbits) const
Create a new 16-bit value expression from a 16-bit value.
SgAsmRegisterReferenceExpression * makeFpRegister(rose_addr_t insn_va, unsigned regnum) const
Create a new floating point register reference expression.
SgAsmRegisterReferenceExpression * makeCp0Register(rose_addr_t insn_va, unsigned regnum, unsigned sel) const
Create a new register reference for Coprocessor 0.