ROSE  0.11.50.0
InstructionEnumsAarch32.h
1 #ifndef ROSE_BinaryAnalysis_InstructionEnumsAarch32_H
2 #define ROSE_BinaryAnalysis_InstructionEnumsAarch32_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_ASM_AARCH32
5 
6 #include <capstone/arm.h>
7 
8 namespace Rose {
9 namespace BinaryAnalysis {
10 
11 using ::arm_insn; // from capstone
12 using Aarch32InstructionKind = ::arm_insn;
14 using ::arm_cc;
15 using Aarch32InstructionCondition = ::arm_cc;
18 enum Aarch32Exception {
19  aarch32_exception_svc,
20  aarch32_exception_udf,
21  aarch32_exception_hvc
22 };
23 
25 enum Aarch32RegisterClass {
26  aarch32_regclass_gpr,
27  aarch32_regclass_sys,
28  aarch32_regclass_ext,
29  aarch32_regclass_coproc,
30  aarch32_regclass_debug
31 };
32 
34 enum Aarch32GeneralPurposeRegister {
35  aarch32_gpr_sb = 9,
36  aarch32_gpr_sl = 10,
37  aarch32_gpr_fp = 11,
38  aarch32_gpr_ip = 12, // not the instruction pointer
39  aarch32_gpr_sp = 13,
40  aarch32_gpr_lr = 14,
41  aarch32_gpr_pc = 15
42 };
43 
45 enum Aarch32DebugRegister {
46  // These numbers are specified in the ARM documentation
47  aarch32_debug_didr = 0,
48  // 1 - 5 is reserved
49  aarch32_debug_wfar = 6,
50  aarch32_debug_vcr = 7,
51  // 8 reserved
52  aarch32_debug_ecr = 9,
53  aarch32_debug_dsccr = 10,
54  aarch32_debug_dsmcr = 11,
55  // 12 - 31 are reserved
56  aarch32_debug_dtrrx = 32,
57  aarch32_debug_itr = 33,
58  aarch32_debug_dscr = 34,
59  aarch32_debug_dtrtx = 35,
60  aarch32_debug_drcr = 36,
61  // 37 - 63 are reserved
62  aarch32_debug_bvr0 = 64,
63  // 65 - 79 are the other 15 BVR registers
64  aarch32_debug_bcr0 = 80,
65  // 81 - 95 are the other 15 BCR registers
66  aarch32_debug_wvr0 = 96,
67  // 97 - 111 are the other 15 WVR registers
68  aarch32_debug_wcr0 = 112,
69  // 128 - 191 are reserved
70  aarch32_debug_oslar = 192,
71  aarch32_debug_oslsr = 193,
72  aarch32_debug_ossrr = 194,
73  // 195 reserved
74  aarch32_debug_prcr = 196,
75  aarch32_debug_prsr = 197,
76  // 198 - 511 are reserved
77  // 512 - 575 are implementation defined
78  // 576 - 831 are reserved
79  // 832 - 895 are processor identification registers (no names given in documentation)
80  // 896 - 927 are reserved
81  // 928 - 959 are implementation defined
82  aarch32_debug_itctrl = 960,
83  // 961 -999 are reserved for management register expansion
84  aarch32_debug_claimset = 1000,
85  aarch32_debug_claimclr = 1001,
86  // 1002 - 1003 are reserved
87  aarch32_debug_lar = 1004,
88  aarch32_debug_lsr = 1005,
89  aarch32_debug_authstatus = 1006,
90  // 1007 - 1009 are reserved
91  aarch32_debug_devid = 1010,
92  aarch32_debug_devtype = 1011,
93  aarch32_debug_peripheralid0 = 1012,
94  aarch32_debug_componentid0 = 1020,
96  // These registers have their register number specified as "N/A" in the documentation: "These registers are only
97  // implemented through the Baseline CP14 Interface and do not have register numbers or offsets."
98  aarch32_debug_drar = 2000,
99  aarch32_debug_dsar
100 };
101 
103 enum Aarch32SystemRegister {
104  aarch32_sys_r8_usr,
105  aarch32_sys_r8_fiq,
106  aarch32_sys_r9_usr,
107  aarch32_sys_r9_fiq,
108  aarch32_sys_r10_usr,
109  aarch32_sys_r10_fiq,
110  aarch32_sys_r11_usr,
111  aarch32_sys_r11_fiq,
112  aarch32_sys_r12_usr,
113  aarch32_sys_r12_fiq,
114  aarch32_sys_sp_hyp,
115  aarch32_sys_sp_svc,
116  aarch32_sys_sp_abt,
117  aarch32_sys_sp_und,
118  aarch32_sys_sp_mon,
119  aarch32_sys_sp_irq,
120  aarch32_sys_sp_fiq,
121  aarch32_sys_sp_usr,
122  aarch32_sys_lr_svc,
123  aarch32_sys_lr_abt,
124  aarch32_sys_lr_und,
125  aarch32_sys_lr_mon,
126  aarch32_sys_lr_irq,
127  aarch32_sys_lr_fiq,
128  aarch32_sys_lr_usr,
129  aarch32_sys_cpsr,
130  aarch32_sys_apsr,
131  aarch32_sys_spsr, // not really a hardware register: stand in for aarch32_sys_spsr_*
132  aarch32_sys_spsr_hyp,
133  aarch32_sys_spsr_svc,
134  aarch32_sys_spsr_abt,
135  aarch32_sys_spsr_und,
136  aarch32_sys_spsr_mon,
137  aarch32_sys_spsr_irq,
138  aarch32_sys_spsr_fiq,
139  aarch32_sys_ipsr,
140  aarch32_sys_iepsr,
141  aarch32_sys_iapsr,
142  aarch32_sys_eapsr,
143  aarch32_sys_psr,
144  aarch32_sys_msp,
145  aarch32_sys_psp,
146  aarch32_sys_primask,
147  aarch32_sys_control,
148  aarch32_sys_fpsid,
149  aarch32_sys_fpscr,
150  aarch32_sys_fpexc,
151  aarch32_sys_fpinst,
152  aarch32_sys_fpinst2,
153  aarch32_sys_mvfr0,
154  aarch32_sys_mvfr1,
155  aarch32_sys_mvfr2,
156  aarch32_sys_itstate,
157  aarch32_sys_unknown // not really a hardware register; used internally by ROSE
158 };
159 
160 } // namespace
161 } // namespace
162 
163 #endif
164 #endif
Main namespace for the ROSE library.