1 #ifndef ROSE_BinaryAnalysis_InstructionEnumsCil_H
2 #define ROSE_BinaryAnalysis_InstructionEnumsCil_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
12 namespace BinaryAnalysis {
222 Cil_unknown_instruction,
526 Cil_mono_ldnativeobj,
530 Cil_mono_restore_lmf,
536 Cil_mono_memory_barrier,
539 Cil_mono_jit_icall_addr,
540 Cil_mono_ldptr_int_req_flag,
541 Cil_mono_ldptr_card_table,
542 Cil_mono_ldptr_nursery_start,
543 Cil_mono_ldptr_nursery_bits,
544 Cil_mono_calli_extra_arg,
546 Cil_mono_atomic_store_i4,
547 Cil_mono_save_last_error,
548 Cil_mono_get_rgctx_arg,
549 Cil_mono_ldptr_profiler_allocation_count,
550 Cil_mono_ld_delegate_method_ptr,
553 Cil_mono_methodconst,
554 Cil_mono_pinvoke_addr_cache,
Access control register 2 (instruction).
Interrupt vector base address.
Address register indirect with post increment: (An)+.
CilEffectiveAddressMode
M68k effective addressing modes.
RAM base address register 1.
Program counter memory indirect post indexed.
CilFamily
Members of the Motorola Coldfire family of m68k processors.
96-bit floating point, "extended real".
Access control register 1 (data).
Address register direct: An.
Multiprocessor control register.
MAC 32-bit accumulator #2.
Program counter memory indirect pre indexed.
ROM base address register 0.
RAM 1 permutation control register 3.
Extensions for ACC0 and ACC1.
CilMacRegister
CIL MAC registers.
Memory indirect post indexed.
RAM 0 permutation control register 3.
Program counter indirect with scaled index and base displacement.
Register indirect addressing modes.
CilInstructionKind
CIL instruction types.
ROM base address register 1.
RAM 0 permutation control register 2.
MAC 32-bit accumulator #1.
Floating-point status register.
MMU base address register.
Main namespace for the ROSE library.
Special purpose registers.
RAM base address register 0.
RAM 1 permutation control register 1.
Program counter indirect.
Data register direct: Dn.
Embedded DRAM base address register.
Floating-point control register.
CilSpecialPurposeRegister
CIL special purpose registers.
Absolute data addressing long: (xxx).L.
Multiply-accumulate registers (includes EMAC registers).
32-bit floating point, "single real".
Address register indirect with pre decrement: -(An)
Program counter indirect with scaled index and 8-bit displacement.
Floating-point instruction address register.
Access control register 3 (instruction).
MAC 32-bit accumulator #3.
Address register indirect with scaled index and base displacement.
CilDataFormat
M68k data formats for floating-point operations.
Three 32-bit words of binary coded decimal.
Status register, including condition codes.
RAM 1 permutation control register 2.
Address register indirect with scaled index.
Program counter memory indirect.
CilSupervisorRegister
CIL supervisor registers.
64-bit floating point, "double real".
Address register indirect: (An)
Memory indirect pre indexed.
Absolute data addressing.
CilRegisterClass
CIL register classes (unclear if these exist)
Alterable addressing modes.
All CIL Instruction sets.
Program counter indirect with displacement: (d_16,PC)
Address register indirect with displacement: (d_16,An)
Address space ID register.
Extensions for ACC2 and ACC3.
RAM 0 permutation control register 1.
Absolute data addressing short: (xxx).W.
Supervisor stack pointer.
Secondary module base address register.
CilEmacRegister
CIL EMAC registers.
Access control register 0 (data).
All register direct addressing modes.
MAC 32-bit accumulator #0.
Module base address register.
Register direct addressing modes.
Memory indirect addressing modes.
Address register indirect with scaled index and 8-bit displacement.
Control addressing modes.
Floating point registers.
Addressing modes specific to m680{20,30,40}.
Program counter indirect with index.