ROSE  0.9.11.42
InstructionEnumsMips.h
1 /* Enum constants for MIPS architectures */
2 #ifndef ROSE_BinaryAnalysis_InstructionEnumsMips_H
3 #define ROSE_BinaryAnalysis_InstructionEnumsMips_H
4 
5 namespace Rose {
6 namespace BinaryAnalysis {
7 
18 };
19 
26 };
27 
35 };
36 
39  mips_unknown_instruction,
349  mips_last_instruction // must be last enum member
350 };
351 
352 } // namespace
353 } // namespace
354 
355 #endif
Rotate word right variable.
Floating point floor convert to word fixed point.
Store conditional word EVA.
Floating point truncate to long fixed point.
Floating point compare not greater than single precision.
Jump register with hazard barrier.
Fixed point ceiling convert to long fixed point.
Branch on COP2 false likely.
Floating point compare not greater than or equal double precision.
Wait for the LLBit to clear.
Floating point compare signaling false double precision.
Floating point truncate to word fixed point.
Floating point compare unordered or less than or equal double precision.
Floating point convert to double floating point.
Floating point compare signaling false single precision.
General purpose registers for coprocessor 0.
Floating point multiply add.
Floating point move conditional on zero.
Execution hazard barrier.
Floating point implementation and revision register.
Floating point compare unordered single precision.
Branch on greater than or equal to zero and link likely.
Count leading zeros in word.
Floating point convert to word fixed point.
Floating point convert to long fixed point.
Floating point negative multiply add.
Floating point compare false pair of single precision.
Fixed point ceiling convert to long fixed point.
Trap if greater or equal.
Multiply and subtract word.
Floating point compare unordered equal.
Move control word to floating point.
Floating point compare not greater than or less than or equal pair of single precision.
Load doubleword to floating point.
Floating point compare less than single precision.
Floating point move conditional on floating point true.
Add immediate unsigned word.
Shift right logical value.
Floating point align variable pair of single precision.
Move floating point conditional on not zero.
Branch on less than zero and link likely.
Load doubleword to coprocessor 2.
Synchronize caches to make instruction writes effective.
Floating point compare ordered or less than or equal single precision.
Move floating point conditional on not zero.
Move conditional on floating point false.
Floating point convert pair lower to single floating point.
Count leading ones in word.
Floating point convert to single floating point.
Store doubleword indexed unaligned from floating point.
Floating point convert pair upper to single floating point.
Bits that compose the FP enables register.
Set on less than unsigned.
Floating point compare ordered or less than pair of single precision.
Store word indexed from floating point.
Floating point absolute value single precision.
Move floating point conditional on not zero.
Floating point compare unordered equal.
Branch on less than zero likely.
Floating point compare false double precision.
Floating point compare equal single precision.
Multiply and add unsigned word to hi, lo.
Shift word left logical variable.
Floating point compare not greater than or less than pair of single precision.
Floating point negative multply subtract.
Load halfword unsigned EVA.
Move conditional on not zero.
Floating point convert to single floating point.
Bitwise logical AND immediate.
Floating point compare unordered pair of single precision.
Floating point compare not greater than or less than single precision.
Move word to coprocessor 2.
Floating point compare unordered or less than pair of single precision.
Floating point compare not greater than or equal pair of single precision.
Floating point floor convert to long fixed point.
Main namespace for the ROSE library.
Floating point floor convert to long fixed point.
Store doubleword indexed from floating point.
Set on less than immediate unsigned.
Move conditional on zero.
Floating point convert to paired single.
Probe TLB for matching entry.
Load word to coprocessor 2.
Floating point absolute value double precision.
Floating point compare equal pair of single precision.
Shift word right arithmetic variable.
Load word to floating point.
Move word from high half of floating point register.
Trap if greater or equal immediate unsigned.
Floating point compare unordered equal.
Floating point compare unordered or less than or equal single precision.
Floating point convert to word fixed point.
Floating point compare ordered or less than or equal pair of single precision.
Floating point add double precision.
Floating point compare less than or equal pair of single precision.
Floating point move conditional on floating point true.
Floating point compare unordered or less than or equal pair of single precision.
Floating point compare unordered or less than single precision.
Floating point compare unordered or less than double precision.
Move control word from floating point.
Floating point multiply add.
Load doubleword indexed to floating point.
Move control word to coprocessor 2.
Coprocessor operation to coprocessor 2.
Floating point negative multply subtract.
Floating point move conditional on floating point false.
MipsSpecialPurposeRegister
MIPS special purpose register minor numbers.
Branch on not equal likely.
Floating point control/status register.
Floating point compare not greater than pair of single precision.
Floating point compare signaling false pair of single precision.
Floating point floor convert to word fixed point.
Floating point absolute value pair of single precision.
Floating point add single precision.
Floating point round to long fixed point.
Floating point compare not greater than double precision.
Trap if less than immediate.
Trap if not equal immediate.
Branch on COP2 true likely.
Floating point round to word fixed point.
Floating point negative multiply add.
Floating point convert to long fixed point.
Trap if greater or equal unsigned.
Store word from coprocessor 2.
Floating point multiply add.
Floating point truncate to word fixed point.
Bits that compose the FP exceptions register.
Trap if less than unsigned.
Floating point square root.
Move word from coprocessor 2.
Branch on greater than zero likely.
Floating point compare less than double precision.
Floating point negative multply subtract.
Move word to floating point.
Floating point compare less than pair of single precision.
Floating point convert to single floating point.
MipsRegisterClass
MIPS major register numbers.
Reciprocal square root approximation.
Branch on greater than or equal to zero likely.
Floating point compare ordered or less than or equal double precision.
Reciprocal square root approximation.
Multiply and add word to hi, lo.
MipsInstructionKind
Kinds of MIPS instructions.
Floating point compare signaling equal pair of single precision.
Floating point compare equal double precision.
Floating point convert to double floating point.
Branch on greater than or equal to zero.
Fixed point ceiling convert to word fixed point.
Floating point multiple and subtract.
Move word to high half of floating point register.
Floating point compare ordered or less than single precision.
Floating point compare not greater than or equal single precision.
Shadow general purpose registers.
Store word from floating point.
Bits that compose the FP condition codes register.
Store doubleword from floating point.
Floating point compare not greater than or less than double precision.
Floating point multiple and subtract.
Multiply and subtract word to hi, lo.
Floating point convert to double floating point.
Load word indexed to floating point.
Floating point compare less than or equal single precision.
Floating point compare not greater than or less than or equal double precision.
Move conditional on floating piont true.
Floating point square root.
Branch on FP true likely.
Floating point move conditional on floating point false.
MipsFcsrMinors
Portions of the FCSR register.
Word swap bytes within halfwords.
Move control word from coprocessor 2.
Floating point round to word fixed point.
Floating point compare signaling equal double precision.
Floating point move conditional on zero.
Move word from coprocessor 1.
Move word to high half of coprocessor 2 register.
Fixed point ceiling convert to word fixed point.
Floating point move conditional on floating point false.
Branch on less than or equal to zero likely.
Floating point add pair of single precision.
Jump and link register with hazard barrier.
Floating point move conditional on zero.
Branch on greater than zero.
Floating point round to long fixed point.
Floating point move conditional on floating point true.
Branch on less than zero and link.
Load doubleword indexed unaligned to floating point.
Floating point compare false single precision.
Coprocessor 2 general purpose registers.
Shift word right arithmetic.
Read GPR from previous shadow set.
Floating point negative multiply add.
Coprocessor 2 special purpose (i.e., control) registers.
Move word from high half of coprocessor 2.
Set on less than immediate.
Branch on less than or equal to zero.
Branch on less than zero.
Floating point compare not greater than or less than or equal single precision.
Trap if less than immediate unsigned.
Store doubleword from coprocessor 2.
Floating point multiple and subtract.
Floating point compare signaling equal single precision.
Write to GPR in previous shadow set.
Trap if greater or equal immediate.
Perform cache operation EVA.
Branch on FP false likely.
Floating point truncate to long fixed point.
Branch on greater than or equal to zero and link.
Floating point compare less than or equal double precision.
Floating point compare unordered double precision.
Floating point control/status register (used to be known as FCR31)
Floating point compare ordered or less than double precision.