ROSE  0.10.5.0
InstructionEnumsX86.h
1 /* Enum constants for Intel x86 architectures */
2 
3 #ifndef ROSE_BinaryAnalysis_InstructionEnumsX86_H
4 #define ROSE_BinaryAnalysis_InstructionEnumsX86_H
5 
6 #include <rosePublicConfig.h>
7 #ifdef ROSE_BUILD_BINARY_ANALYSIS_SUPPORT
8 
9 #include "AssemblerX86Init.h" /* A big enum whose members are all possible x86 instructions. */
10 
11 namespace Rose {
12 namespace BinaryAnalysis {
13 
16  x86_insnsize_none,
20 };
21 
33 };
34 
37  x86_segreg_es = 0, // Numbering is based on Intel documentation
38  x86_segreg_cs = 1,
39  x86_segreg_ss = 2,
40  x86_segreg_ds = 3,
41  x86_segreg_fs = 4,
42  x86_segreg_gs = 5,
43  x86_segreg_none = 16 /* For unspecified segment overrides */
44 };
45 
48  x86_gpr_ax = 0, // Numbering is based on Intel documentation
49  x86_gpr_cx = 1,
50  x86_gpr_dx = 2,
51  x86_gpr_bx = 3,
52  x86_gpr_sp = 4,
53  x86_gpr_bp = 5,
54  x86_gpr_si = 6,
55  x86_gpr_di = 7,
56  x86_gpr_r8 = 8,
57  x86_gpr_r9 = 9,
58  x86_gpr_r10 = 10,
59  x86_gpr_r11 = 11,
60  x86_gpr_r12 = 12,
61  x86_gpr_r13 = 13,
62  x86_gpr_r14 = 14,
63  x86_gpr_r15 = 15
64 };
65 
68  x86_st_0 = 0,
69  x86_st_1 = 1,
70  x86_st_2 = 2,
71  x86_st_3 = 3,
72  x86_st_4 = 4,
73  x86_st_5 = 5,
74  x86_st_6 = 6,
75  x86_st_7 = 7,
76  x86_st_nregs = 8 // number of ST registers
77 };
78 
80 enum X86Flags {
81  x86_flags_status = 0, // general-purpose status flags
82  x86_flags_fpstatus = 1, // floating-point status flags
83  x86_flags_fptag = 2, // floating-point tag register
84  x86_flags_fpctl = 3, // floating-point control register
85  x86_flags_mxcsr = 4 // SSE control and status register
86 };
87 
89 enum X86Flag {
90  x86_flag_cf = 0,
91  x86_flag_pf = 2,
92  x86_flag_af = 4,
93  x86_flag_zf = 6,
94  x86_flag_sf = 7,
95  x86_flag_tf = 8,
96  x86_flag_if = 9,
97  x86_flag_df = 10,
98  x86_flag_of = 11,
99  x86_flag_iopl = 12, /* 2 bits, 12 and 13 */
100  x86_flag_nt = 14,
101  x86_flag_rf = 16,
102  x86_flag_vm = 17,
103  x86_flag_ac = 18,
104  x86_flag_vif = 19,
105  x86_flag_vip = 20,
106  x86_flag_id = 21
107 };
108 
111 {
112  x86_branch_prediction_none,
113  x86_branch_prediction_taken,
114  x86_branch_prediction_not_taken
115 };
116 
119 {
123 };
124 
154 };
155 
156 } // namespace
157 } // namespace
158 
159 #endif
160 #endif
Instruction pointer; Only allowed minor is zero.
Instruction is for a 64-bit architecture.
Minors are X86GeneralPurposeRegister (ax,cx,dx,bx,sp,bp,si,di,r8..r15)
Floating point stack or MM registers; Minors are 0-7.
128-bit xmmN; Minors are 0-7.
X86RegisterClass
Intel x86 major register numbers.
X86BranchPrediction
Intel x86 branch prediction types.
Minors are X86SegmentRegister (es,cs,ss,ds,fs,gs)
Control registers; Minors are 0-4, 8.
Main namespace for the ROSE library.
X86GeneralPurposeRegister
Intel x86 general purpose registers.
X86Flag
Intel x86 status flags.
Device not available (no math coproc).
Debug registers; Minors are 0-7.
Instruction is for a 32-bit architecture.
Instruction is for a 16-bit architecture.
Repeat not equal prefix 0xf2.
X86SegmentRegister
Intel x86 segment registers.
X86StRegister
Intel x86 ST-related registers.
SIMD floating-point numeric error.
X86Exception
Protected mode exceptions.
X86InstructionSize
Intel x86 instruction size constants.
X86RepeatPrefix
Intel x86 instruction repeat prefix.
Floating point error (math fault).
X86Flags
Minor numbers for x86_regclass_flag.