ROSE  0.11.2.0
InstructionEnumsA64.h
1 #ifndef ROSE_BinaryAnalysis_InstructionEnumsArm_H
2 #define ROSE_BinaryAnalysis_InstructionEnumsArm_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_ASM_A64
5 
6 #include <capstone/arm64.h>
7 #include <string>
8 
9 namespace Rose {
10 namespace BinaryAnalysis {
11 
12 using ::arm64_insn;
13 using A64InstructionKind = ::arm64_insn;
15 using ::arm64_cc;
16 using A64InstructionCondition = ::arm64_cc;
18 using ::arm64_extender;
19 using A64Extender = ::arm64_extender;
21 using ::arm64_vas;
22 using A64VectorArrangement = ::arm64_vas;
24 using ::arm64_at_op;
25 using A64AtOperation = ::arm64_at_op;
27 using ::arm64_prefetch_op;
28 using A64PrefetchOperation = ::arm64_prefetch_op;
30 using ::arm64_barrier_op;
31 using A64BarrierOperation = ::arm64_barrier_op;
34 enum class A64Exception {
35  brk
36 };
37 
39 enum A64RegisterClass {
40  arm_regclass_gpr, // general purpose registers
41  arm_regclass_sp, // stack pointer registers
42  arm_regclass_ext, // SIMD and FP registers, so-called "extension" registers
43  arm_regclass_pc, // program counter, instruction pointer
44  arm_regclass_cc, // condition codes registers
45  arm_regclass_system, // system registers
46 };
47 
54 enum A64SystemRegisters {
55  arm_system_actlr = 0, // auxiliary control registers
56  arm_system_ccsidr = 4, // current cache size ID registers
57  arm_system_clidr = 8, // cache level ID registers
58  arm_system_cntfrq = 12, // counter-timer frequency registers
59  arm_system_cntpct = 16, // counter-timer physical count registers
60  arm_system_cntkctl = 20, // counter-timer kernel control registers
61  arm_system_cntp_cval = 24, // counter-timer physical timer compare registers
62  arm_system_cpacr = 28, // coprocessor access control registers
63  arm_system_csselr = 32, // cache size selection registers
64  arm_system_cntp_ctl = 36, // counter-timer physical control registers
65  arm_system_ctr = 40, // cache type registers
66  arm_system_dczid = 44, // data cache zero ID registers
67  arm_system_elr = 48, // exception link registers
68  arm_system_esr = 52, // exception syndrome registers
69  arm_system_far = 56, // fault address registers
70  arm_system_hcr = 60, // hypervisor configuration registers
71  arm_system_mair = 64, // memory attribute indirection registers
72  arm_system_midr = 68, // main ID registers
73  arm_system_mpidr = 72, // multiprocessor affinity registers
74  arm_system_scr = 76, // secure configuration registers
75  arm_system_sctlr = 80, // system control registers
76  arm_system_spsr = 84, // saved program status registers
77  arm_system_tcr = 88, // translation control registers
78  arm_system_tpidr = 92, // user read/write thread ID registers
79  arm_system_tpidrr0 = 96, // user read-only thread ID registers
80  arm_system_ttbr0 = 100, // translation table base registers 0
81  arm_system_ttbr1 = 104, // translation table base register 1
82  arm_system_vbar = 108, // vector based address registers
83  arm_system_vtcr = 112, // virtualization translation control registers
84  arm_system_vttbr = 116 // virtualization translation table base registers
85 };
86 
87 } // namespace
88 } // namespace
89 
90 #endif
91 #endif
const char * A64SystemRegisters(int64_t)
Convert Rose::BinaryAnalysis::A64SystemRegisters enum constant to a string.
Definition: stringify.C:41069
Main namespace for the ROSE library.
const char * A64RegisterClass(int64_t)
Convert Rose::BinaryAnalysis::A64RegisterClass enum constant to a string.
Definition: stringify.C:41011