1#ifndef ROSE_BinaryAnalysis_InstructionSemantics_BaseSemantics_Dispatcher_H
2#define ROSE_BinaryAnalysis_InstructionSemantics_BaseSemantics_Dispatcher_H
3#include <featureTests.h>
4#ifdef ROSE_ENABLE_BINARY_ANALYSIS
6#include <Rose/BinaryAnalysis/BasicTypes.h>
8#include <boost/enable_shared_from_this.hpp>
9#include <boost/serialization/access.hpp>
10#include <boost/serialization/export.hpp>
11#include <boost/serialization/nvp.hpp>
12#include <boost/serialization/shared_ptr.hpp>
15namespace BinaryAnalysis {
16namespace InstructionSemantics {
43class Dispatcher:
public boost::enable_shared_from_this<Dispatcher> {
57 typedef std::vector<InsnProcessor*> InsnProcessors;
58 InsnProcessors iproc_table;
60#ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
62 friend class boost::serialization::access;
65 void serializeCommon(S &s,
const unsigned version) {
66 ASSERT_always_require(version >= 2);
67 s & boost::serialization::make_nvp(
"operators", operators_);
73 void save(S &s,
const unsigned version)
const {
74 const_cast<Dispatcher*
>(
this)->serializeCommon(s, version);
75 ASSERT_not_null(architecture_);
81 void load(S &s,
const unsigned version) {
82 serializeCommon(s, version);
88 BOOST_SERIALIZATION_SPLIT_MEMBER();
102 virtual ~Dispatcher();
Dispatches instructions through the RISC layer.
virtual void operators(const RiscOperatorsPtr &)
Property: RISC operators.
virtual void initializeState(const StatePtr &)
Initialize the state.
Architecture::BaseConstPtr architecture() const
Property: Architecture.
virtual InsnProcessor * iprocLookup(SgAsmInstruction *insn)
Lookup the processor for an instruction.
virtual RegisterDescriptor stackPointerRegister() const
Returns the stack pointer register.
virtual void postUpdate(SgAsmExpression *, const BaseSemantics::SValuePtr &enabled)
Update registers for post-add expressions.
virtual SValuePtr protoval() const
Return the prototypical value.
bool autoResetInstructionPointer_
Reset instruction pointer register for each instruction.
virtual void preUpdate(SgAsmExpression *, const BaseSemantics::SValuePtr &enabled)
Update registers for pre-add expressions.
virtual SValuePtr unspecified_(size_t nbits) const
Return a new undefined semantic value.
virtual SValuePtr read(SgAsmExpression *, size_t value_nbits=0, size_t addr_nbits=0)
Reads an R-value expression.
virtual StatePtr currentState() const
Get a pointer to the state object.
virtual RegisterDescriptor stackFrameRegister() const
Returns the stack call frame register.
virtual int iprocKey(SgAsmInstruction *) const =0
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table.
virtual SValuePtr number_(size_t nbits, uint64_t number) const
Return a semantic value representing a number.
virtual RegisterDescriptor callReturnRegister() const
Returns the function call return address register.
virtual void incrementRegisters(SgAsmExpression *)
Increment all auto-increment registers in the expression.
virtual SValuePtr undefined_(size_t nbits) const
Return a new undefined semantic value.
virtual void decrementRegisters(SgAsmExpression *)
Decrement all auto-decrement registers in the expression.
virtual InsnProcessor * iprocGet(int key)
Obtain an iproc table entry for the specified key.
virtual RegisterDescriptor findRegister(const std::string ®name, size_t nbits=0, bool allowMissing=false) const
Lookup a register by name.
virtual SValuePtr effectiveAddress(SgAsmExpression *, size_t nbits=0)
Returns a memory address by evaluating the address expression.
bool autoResetInstructionPointer() const
Property: Reset instruction pointer register for each instruction.
virtual void iprocReplace(SgAsmInstruction *insn, InsnProcessor *iproc)
Replace an instruction processor with another.
virtual void processInstruction(SgAsmInstruction *insn)
Process a single instruction.
size_t addressWidth() const
Property: Width of memory addresses in bits.
DispatcherPtr Ptr
Shared-ownership pointer.
virtual SgAsmInstruction * currentInstruction() const
Returns the instruction that is being processed.
virtual void write(SgAsmExpression *, const SValuePtr &value, size_t addr_nbits=0)
Writes to an L-value expression.
virtual void advanceInstructionPointer(SgAsmInstruction *)
Update the instruction pointer register.
virtual DispatcherPtr create(const RiscOperatorsPtr &ops) const =0
Virtual constructor.
void autoResetInstructionPointer(bool b)
Property: Reset instruction pointer register for each instruction.
virtual RegisterDescriptor segmentRegister(SgAsmMemoryReferenceExpression *)
Returns a register descriptor for the segment part of a memory reference expression.
virtual void iprocSet(int key, InsnProcessor *iproc)
Set an iproc table entry to the specified value.
RegisterDictionaryPtr registerDictionary() const
Property: Register dictionary.
virtual RegisterDescriptor instructionPointerRegister() const
Returns the instruction pointer register.
virtual RiscOperatorsPtr operators() const
Property: RISC operators.
Functor that knows how to dispatch a single kind of instruction.
Describes (part of) a physical CPU register.
Base class for expressions.
Base class for machine instructions.
Reference to memory locations.
const std::string & name(const BaseConstPtr &)
Architecture name free function.
std::shared_ptr< const Base > BaseConstPtr
Reference counted pointer for Architecture::Base.
Sawyer::Result< BasePtr, NotFound > findByName(const std::string &)
Look up a new architecture by name.
Base classes for instruction semantics.
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
boost::shared_ptr< State > StatePtr
Shared-ownership pointer to a semantic state.