1 #ifndef ROSE_BinaryAnalysis_InstructionEnumsPowerpc_H
2 #define ROSE_BinaryAnalysis_InstructionEnumsPowerpc_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
9 namespace BinaryAnalysis {
19 powerpc_unknown_instruction = 0,
461 powerpc_last_instruction
466 powerpc_regclass_unknown,
493 powerpc_spr_dsisr = 18,
494 powerpc_spr_dar = 19,
501 powerpc_tbr_tbl = 268,
502 powerpc_tbr_tbu = 269
Store Floating-Point as Integer Word Indexed (optional).
Rotate Left Doubleword then Clear Left.
PowerpcSpecialPurposeRegister
PowerPC special purpose registers.
Divide Doubleword Unsigned.
Branch Conditional to Count Register.
Trap Doubleword Immediate.
Floating-Point Select (optional).
Subtract from Zero Extended.
Rotate Left Doubleword Immediate then Clear Left.
Load Byte and Zero with Update.
Add Immediate Carrying and Record.
Floating-Point Select (optional).
Multiply High Doubleword Unsigned.
Rotate Left Doubleword Immediate then Clear Right.
Floating Negative Multiply-Add Single.
Floating Reciprocal Estimate Single (optional).
Move from Segment Register Indirect.
Rotate Left Doubleword then Clear Right.
Floating-Point Square Root (optional).
Translation Look-aside Buffer Synchronize (optional).
Count Leading Zeros Doubleword.
Condition Register (only particular fields or bits may be used).
Move to FPSCR Field Immediate.
Floating Reciprocal Estimate Single (optional).
Enforce In-order Execution of I/O.
Rotate Left Doubleword Immediate then Clear Right.
Rotate Left Doubleword then Clear Left.
Store String Word Indexed.
FP2 Floating Parallel Multiply (BGL specific).
Data Cache Block Touch for Store.
processor version register.
Shift Right Algebraic Doubleword.
Move from Special-Purpose Register.
Shift Right Algebraic Word Immediate.
Floating Convert to Integer Word.
Multiply High Doubleword.
Subtract from Zero Extended.
FP2 Floating Cross Copy-Primary Multiply (BGL specific).
Floating Convert from Integer Doubleword.
Shift Right Algebraic Word.
Condition Register AND with Complement.
Load Half and Zero Indexed.
Load Floating-Point Single Indexed.
Store Floating-Point Single.
Data Stream Touch for store.
Time base register (0..1023).
Store Byte with Update Indexed.
FP2 Floating Parallel Subtract (BGL specific).
Data Stream Touch for store.
FP2 Floating Parallel Add (BGL specific).
Add to Minus One Extended.
Last FP2 specific enum value.
Rotate Left Doubleword Immediate then Mask Insert.
Subtract from Zero Extended.
Branch Conditional Link Register.
Store Floating-Point Single with Update Indexed.
Load Floating-Point Double Indexed.
FP2 Floating Parallel Reciprocal Estimate (BGL specific).
Load Floating-Point Double.
Count Leading Zeros Word.
Move to Special-Purpose Register.
Rotate Left Doubleword Immediate then Clear.
Subtract from Minus One Extended.
Subtract from Immediate Carrying.
Shift Right Algebraic Doubleword Immediate.
Floating Round to Single Precision.
Floating Reciprocal Square Root Estimate (optional).
Floating-Point Square Root (optional).
Floating Negative Multiply-Add Single.
Floating Negative Multiply-Subtract Single.
Load Floating-Point Single with Update Indexed.
Main namespace for the ROSE library.
Move to Segment Register.
Store Word Byte-Reversed Indexed.
Store Doubleword Indexed.
Load Half Algebraic with Update Indexed.
Load Floating-Point Single.
Floating Reciprocal Estimate Single (optional).
Store Floating-Point Single Indexed.
Move to Segment Register Indirect.
Move to Machine State Register.
Load Word and Zero Indexed.
Multiply High Word Unsigned.
PowerpcInstructionKind
PowerPC instruction types.
Load Half Algebraic with Update.
Divide Doubleword Unsigned.
Move to Segment Register.
Load Word Algebraic Indexed.
Floating Negative Multiply-Subtract Single.
Store Word Conditional Indexed.
Add to Minus One Extended.
Move to Condition Register from FPSCR.
Floating Reciprocal Square Root Estimate (optional).
Move to Machine State Register.
Floating Reciprocal Square Root Estimate (optional).
Load Half Byte-Reversed Indexed.
Rotate Left Doubleword Immediate then Mask Insert.
Subtract from Minus One Extended.
Floating Multiply-Add Single.
Load Half and Zero with Update.
Load Word with Zero Update.
Floating Multiply-Subtract Single.
Floating Subtract Single.
Load Floating-Point Double with Update.
Floating Compare Ordered.
Rotate Left Word then AND with Mask.
Floating-Point Square Root (optional).
Load Doubleword with Update.
Floating Negative Multiply-Add.
Rotate Left Doubleword then Clear Right.
Move Condition Register Field.
Floating-Point Register (0..31; 64 bits each).
Move to Condition Register Fields.
External Control out Word Indexed (opt.).
Move from Machine State Register.
Data Cache Block Set to Zero.
Condition Register Equivalent.
Floating Negative Absolute Value.
Load String Word Indexed.
Floating Convert to Integer Word with Round to Zero.
Floating Multiply Single.
Floating Negative Multiply-Subtract.
Load Word Byte-Reversed Indexed.
Load Half Algebraic Indexed.
Move to Segment Register Indirect.
Floating Reciprocal Estimate Single (optional).
Load Half and Zero with Update Indexed.
Store Floating-Point Single with Update.
Floating Multiply-Subtract.
Floating Multiply Single.
Load Word Algebraic with Update Indexed.
Floating Negative Multiply-Subtract.
Move to Condition Register from XER.
Subtract from Minus One Extended.
Special-purpose register (0..1023).
Add to Minus One Extended.
Load Floating-Point Double with Update Indexed.
Subtract from Minus One Extended.
Store Floating-Point Double Indexed.
Store Floating-Point Double with Update Indexed.
Load String Word Immediate.
instruction address (pseudo) register.
Load Word and Reserve Indexed.
Rotate Left Word then AND with Mask.
Floating Convert to Integer Doubleword.
Store Doubleword Conditional Indexed.
Shift Right Algebraic Word Immediate.
Whole CR (or unknown or not using a CR).
Multiply High Doubleword Unsigned.
Load Doubleword with Update Indexed.
Floating point status and control register.
Floating Convert to Integer Doubleword.
Move from Condition Register.
Branch Conditional to Count Register.
PowerpcWordSize
PowerPC word size.
Floating Round to Single Precision.
Floating Convert from Integer Doubleword.
Floating Convert to Integer Word.
Subtract from Zero Extended.
Store Floating-Point Double with Update.
Store Half Byte-Reverse Indexed.
Data Cache Block Invalidate.
Rotate Left Word Immediate then AND with Mask.
General Purpose Register (0..31).
Floating Negative Absolute Value.
Floating-Point Square Root (optional).
Floating Compare Unordered.
Rotate Left Doubleword Immediate then Clear Left.
Instruction Cache Block Invalidate.
Floating Convert to Integer Doubleword with Round Toward Zero.
fixed-point exception register.
Branch Conditional Link Register.
Floating Multiply-Subtract Single.
Rotate Left Word Immediate then Mask Insert.
Store Doubleword with Update.
Floating Negative Multiply-Add.
Data Cache Block Allocate.
Rotate Left Word Immediate then Mask Insert.
FP2 Floating Parallel Reciprocal Square Root Estimate (BGL specific).
Rotate Left Doubleword Immediate then Clear.
Shift Right Algebraic Word.
Count Leading Zeros Word.
Floating Convert to Integer Doubleword with Round Toward Zero.
Shift Right Algebraic Doubleword.
Store Half with Update Indexed.
Multiply High Doubleword.
PowerpcTimeBaseRegister
PowerPC time base registers.
PowerpcConditionRegisterAccessGranularity
PowerPC condition register access granularity.
Floating Convert to Integer Word with Round to Zero.
External Control in Word Indexed (opt.).
Floating Subtract Single.
Store Word with Update Indexed.
FP2 Floating Cross Multiply (BGL specific).
Load Byte and Zero Indexed.
Count Leading Zeros Doubleword.
Add to Minus One Extended.
Move to FPSCR Field Immediate.
Load Doubleword and Reserve Indexed.
Multiply High Word Unsigned.
Divide Doubleword Unsigned.
Condition Register OR with Complement.
Floating Multiply-Subtract.
Load Floating-Point Single with Update.
Store String Word Immediate.
PowerpcRegisterClass
PowerPC register classes.
Compare Logical Immediate.
Shift Right Algebraic Doubleword Immediate.
Load Word and Zero with Update Indexed.
Rotate Left Word Immediate then AND with Mask.
Translation Look-aside Buffer Invalidate All (optional).
Store Floating-Point Double.
Floating Multiply-Add Single.
Store Doubleword with Update Indexed.
Divide Doubleword Unsigned.
Move from Segment Register.
FP2 Floating Cross Copy-Secondary Multiply (BGL specific).
Translation Look-aside Buffer Invalidate Entry (optional).
Load Byte and Zero with Update Indexed.
Floating Reciprocal Square Root Estimate (optional).