ROSE  0.10.5.0
InstructionEnumsPowerpc.h
1 #ifndef ROSE_BinaryAnalysis_InstructionEnumsPowerpc_H
2 #define ROSE_BinaryAnalysis_InstructionEnumsPowerpc_H
3 
4 #include <rosePublicConfig.h>
5 #ifdef ROSE_BUILD_BINARY_ANALYSIS_SUPPORT
6 
7 #include <string>
8 
9 namespace Rose {
10 namespace BinaryAnalysis {
11 
16 };
17 
20  powerpc_unknown_instruction = 0,
175  powerpc_fpmr,
176  powerpc_fpabs,
177  powerpc_lfssx,
178  powerpc_fpneg,
179  powerpc_lfssux,
180  powerpc_fprsp,
181  powerpc_lfsdx,
182  powerpc_fpnabs,
183  powerpc_lfsdux,
184  powerpc_lfxsx,
185  powerpc_fsmr,
186  powerpc_lfxsux,
187  powerpc_lfxdx,
188  powerpc_fsabs,
189  powerpc_lfxdux,
190  powerpc_lfpsx,
191  powerpc_fsneg,
192  powerpc_lfpsux,
193  powerpc_lfpdx,
194  powerpc_fsnabs,
195  powerpc_lfpdux,
196  powerpc_stfpiwx,
197  powerpc_fxmr,
198  powerpc_fpctiw,
199  powerpc_stfssx,
200  powerpc_stfssux,
201  powerpc_fpctiwz,
202  powerpc_stfsdx,
203  powerpc_stfsdux,
204  powerpc_stfxsx,
205  powerpc_fsmtp,
206  powerpc_stfxsux,
207  powerpc_stfxdx,
208  powerpc_stfxdux,
209  powerpc_stfpsx,
210  powerpc_fsmfp,
211  powerpc_stfpsux,
212  powerpc_stfpdx,
213  powerpc_stfpdux,
214  powerpc_fpsel,
215  powerpc_fpmadd,
216  powerpc_fpmsub,
217  powerpc_fxmadd,
218  powerpc_fxcpmadd,
219  powerpc_fxcsmadd,
220  powerpc_fpnmadd,
221  powerpc_fxnmadd,
222  powerpc_fxcpnmadd,
223  powerpc_fxcsnmadd,
224  powerpc_fxcpnpma,
225  powerpc_fxmsub,
226  powerpc_fxcsnpma,
227  powerpc_fxcpmsub,
228  powerpc_fxcpnsma,
229  powerpc_fxcsmsub,
230  powerpc_fxcsnsma,
231  powerpc_fpnmsub,
232  powerpc_fxcxma,
233  powerpc_fxnmsub,
234  powerpc_fxcxnpma,
235  powerpc_fxcpnmsub,
236  powerpc_fxcxnsma,
237  powerpc_fxcsnmsub,
462  powerpc_last_instruction
463 };
464 
467  powerpc_regclass_unknown,
479 };
480 
486 };
487 
490  // These must match the processor's numbers
494  powerpc_spr_dsisr = 18,
495  powerpc_spr_dar = 19,
496  powerpc_spr_dec = 22 // FIXME: fill in the rest of these
497 };
498 
501  // These must match the processor's numbers
502  powerpc_tbr_tbl = 268,
503  powerpc_tbr_tbu = 269
504 };
505 
506 } // namespace
507 } // namespace
508 
509 #endif
510 #endif
Store Floating-Point as Integer Word Indexed (optional).
Rotate Left Doubleword then Clear Left.
PowerpcSpecialPurposeRegister
PowerPC special purpose registers.
Branch Conditional to Count Register.
Rotate Left Doubleword Immediate then Clear Left.
Load Byte and Zero with Update.
Add Immediate Carrying and Record.
Floating-Point Select (optional).
Rotate Left Doubleword Immediate then Clear Right.
Floating Negative Multiply-Add Single.
Floating Reciprocal Estimate Single (optional).
Move from Segment Register Indirect.
Rotate Left Doubleword then Clear Right.
Floating-Point Square Root (optional).
Translation Look-aside Buffer Synchronize (optional).
Count Leading Zeros Doubleword.
Condition Register (only particular fields or bits may be used).
Floating Reciprocal Estimate Single (optional).
Enforce In-order Execution of I/O.
Rotate Left Doubleword Immediate then Clear Right.
Rotate Left Doubleword then Clear Left.
FP2 Floating Parallel Multiply (BGL specific).
Data Cache Block Touch for Store.
Move from Special-Purpose Register.
Shift Right Algebraic Word Immediate.
Floating Convert to Integer Word.
FP2 Floating Cross Copy-Primary Multiply (BGL specific).
Floating Convert from Integer Doubleword.
Condition Register AND with Complement.
Load Floating-Point Single Indexed.
Store Byte with Update Indexed.
FP2 Floating Parallel Subtract (BGL specific).
FP2 Floating Parallel Add (BGL specific).
Rotate Left Doubleword Immediate then Mask Insert.
Branch Conditional Link Register.
Store Floating-Point Single with Update Indexed.
Load Floating-Point Double Indexed.
FP2 Floating Parallel Reciprocal Estimate (BGL specific).
Move to Special-Purpose Register.
Rotate Left Doubleword Immediate then Clear.
Subtract from Minus One Extended.
Subtract from Immediate Carrying.
Shift Right Algebraic Doubleword Immediate.
Floating Round to Single Precision.
Floating Reciprocal Square Root Estimate (optional).
Floating-Point Square Root (optional).
Floating Negative Multiply-Add Single.
Floating Negative Multiply-Subtract Single.
Load Floating-Point Single with Update Indexed.
Main namespace for the ROSE library.
Store Word Byte-Reversed Indexed.
Load Half Algebraic with Update Indexed.
Floating Reciprocal Estimate Single (optional).
Store Floating-Point Single Indexed.
Move to Segment Register Indirect.
Move to Machine State Register.
PowerpcInstructionKind
PowerPC instruction types.
Load Half Algebraic with Update.
Floating Negative Multiply-Subtract Single.
Move to Condition Register from FPSCR.
Floating Reciprocal Square Root Estimate (optional).
Move to Machine State Register.
Floating Reciprocal Square Root Estimate (optional).
Load Half Byte-Reversed Indexed.
Rotate Left Doubleword Immediate then Mask Insert.
Subtract from Minus One Extended.
Load Half and Zero with Update.
Load Floating-Point Double with Update.
Rotate Left Word then AND with Mask.
Floating-Point Square Root (optional).
Rotate Left Doubleword then Clear Right.
Move Condition Register Field.
Floating-Point Register (0..31; 64 bits each).
Move to Condition Register Fields.
External Control out Word Indexed (opt.).
Move from Machine State Register.
Data Cache Block Set to Zero.
Condition Register Equivalent.
Floating Convert to Integer Word with Round to Zero.
Floating Negative Multiply-Subtract.
Load Word Byte-Reversed Indexed.
Move to Segment Register Indirect.
Floating Reciprocal Estimate Single (optional).
Load Half and Zero with Update Indexed.
Store Floating-Point Single with Update.
Load Word Algebraic with Update Indexed.
Floating Negative Multiply-Subtract.
Move to Condition Register from XER.
Special-purpose register (0..1023).
Load Floating-Point Double with Update Indexed.
Store Floating-Point Double Indexed.
Store Floating-Point Double with Update Indexed.
instruction address (pseudo) register.
Load Word and Reserve Indexed.
Rotate Left Word then AND with Mask.
Floating Convert to Integer Doubleword.
Store Doubleword Conditional Indexed.
Shift Right Algebraic Word Immediate.
Multiply High Doubleword Unsigned.
Load Doubleword with Update Indexed.
Floating point status and control register.
Floating Convert to Integer Doubleword.
Move from Condition Register.
Branch Conditional to Count Register.
PowerpcWordSize
PowerPC word size.
Floating Round to Single Precision.
Floating Convert from Integer Doubleword.
Store Floating-Point Double with Update.
Store Half Byte-Reverse Indexed.
Rotate Left Word Immediate then AND with Mask.
Floating Negative Absolute Value.
Floating-Point Square Root (optional).
Rotate Left Doubleword Immediate then Clear Left.
Instruction Cache Block Invalidate.
Floating Convert to Integer Doubleword with Round Toward Zero.
fixed-point exception register.
Branch Conditional Link Register.
Floating Multiply-Subtract Single.
Rotate Left Word Immediate then Mask Insert.
Store Doubleword with Update.
Floating Negative Multiply-Add.
Rotate Left Word Immediate then Mask Insert.
FP2 Floating Parallel Reciprocal Square Root Estimate (BGL specific).
Rotate Left Doubleword Immediate then Clear.
Floating Convert to Integer Doubleword with Round Toward Zero.
Shift Right Algebraic Doubleword.
Store Half with Update Indexed.
PowerpcTimeBaseRegister
PowerPC time base registers.
PowerpcConditionRegisterAccessGranularity
PowerPC condition register access granularity.
Floating Convert to Integer Word with Round to Zero.
External Control in Word Indexed (opt.).
Store Word with Update Indexed.
FP2 Floating Cross Multiply (BGL specific).
Load Doubleword and Reserve Indexed.
Condition Register OR with Complement.
Load Floating-Point Single with Update.
PowerpcRegisterClass
PowerPC register classes.
Shift Right Algebraic Doubleword Immediate.
Load Word and Zero with Update Indexed.
Rotate Left Word Immediate then AND with Mask.
Translation Look-aside Buffer Invalidate All (optional).
Store Doubleword with Update Indexed.
FP2 Floating Cross Copy-Secondary Multiply (BGL specific).
Translation Look-aside Buffer Invalidate Entry (optional).
Load Byte and Zero with Update Indexed.
Floating Reciprocal Square Root Estimate (optional).