ROSE  0.9.12.19
InstructionEnumsPowerpc.h
1 #ifndef ROSE_BinaryAnalysis_InstructionEnumsPowerpc_H
2 #define ROSE_BinaryAnalysis_InstructionEnumsPowerpc_H
3 
4 #include <string>
5 
6 namespace Rose {
7 namespace BinaryAnalysis {
8 
13 };
14 
17  powerpc_unknown_instruction = 0,
172  powerpc_fpmr,
173  powerpc_fpabs,
174  powerpc_lfssx,
175  powerpc_fpneg,
176  powerpc_lfssux,
177  powerpc_fprsp,
178  powerpc_lfsdx,
179  powerpc_fpnabs,
180  powerpc_lfsdux,
181  powerpc_lfxsx,
182  powerpc_fsmr,
183  powerpc_lfxsux,
184  powerpc_lfxdx,
185  powerpc_fsabs,
186  powerpc_lfxdux,
187  powerpc_lfpsx,
188  powerpc_fsneg,
189  powerpc_lfpsux,
190  powerpc_lfpdx,
191  powerpc_fsnabs,
192  powerpc_lfpdux,
193  powerpc_stfpiwx,
194  powerpc_fxmr,
195  powerpc_fpctiw,
196  powerpc_stfssx,
197  powerpc_stfssux,
198  powerpc_fpctiwz,
199  powerpc_stfsdx,
200  powerpc_stfsdux,
201  powerpc_stfxsx,
202  powerpc_fsmtp,
203  powerpc_stfxsux,
204  powerpc_stfxdx,
205  powerpc_stfxdux,
206  powerpc_stfpsx,
207  powerpc_fsmfp,
208  powerpc_stfpsux,
209  powerpc_stfpdx,
210  powerpc_stfpdux,
211  powerpc_fpsel,
212  powerpc_fpmadd,
213  powerpc_fpmsub,
214  powerpc_fxmadd,
215  powerpc_fxcpmadd,
216  powerpc_fxcsmadd,
217  powerpc_fpnmadd,
218  powerpc_fxnmadd,
219  powerpc_fxcpnmadd,
220  powerpc_fxcsnmadd,
221  powerpc_fxcpnpma,
222  powerpc_fxmsub,
223  powerpc_fxcsnpma,
224  powerpc_fxcpmsub,
225  powerpc_fxcpnsma,
226  powerpc_fxcsmsub,
227  powerpc_fxcsnsma,
228  powerpc_fpnmsub,
229  powerpc_fxcxma,
230  powerpc_fxnmsub,
231  powerpc_fxcxnpma,
232  powerpc_fxcpnmsub,
233  powerpc_fxcxnsma,
234  powerpc_fxcsnmsub,
459  powerpc_last_instruction
460 };
461 
464  powerpc_regclass_unknown,
476 };
477 
483 };
484 
487  // These must match the processor's numbers
491  powerpc_spr_dsisr = 18,
492  powerpc_spr_dar = 19,
493  powerpc_spr_dec = 22 // FIXME: fill in the rest of these
494 };
495 
498  // These must match the processor's numbers
499  powerpc_tbr_tbl = 268,
500  powerpc_tbr_tbu = 269
501 };
502 
503 } // namespace
504 } // namespace
505 
506 #endif
Store Floating-Point as Integer Word Indexed (optional).
Rotate Left Doubleword then Clear Left.
PowerpcSpecialPurposeRegister
PowerPC special purpose registers.
Branch Conditional to Count Register.
Rotate Left Doubleword Immediate then Clear Left.
Load Byte and Zero with Update.
Add Immediate Carrying and Record.
Floating-Point Select (optional).
Rotate Left Doubleword Immediate then Clear Right.
Floating Negative Multiply-Add Single.
Floating Reciprocal Estimate Single (optional).
Move from Segment Register Indirect.
Rotate Left Doubleword then Clear Right.
Floating-Point Square Root (optional).
Translation Look-aside Buffer Synchronize (optional).
Count Leading Zeros Doubleword.
Condition Register (only particular fields or bits may be used).
Floating Reciprocal Estimate Single (optional).
Enforce In-order Execution of I/O.
Rotate Left Doubleword Immediate then Clear Right.
Rotate Left Doubleword then Clear Left.
FP2 Floating Parallel Multiply (BGL specific).
Data Cache Block Touch for Store.
Move from Special-Purpose Register.
Shift Right Algebraic Word Immediate.
Floating Convert to Integer Word.
FP2 Floating Cross Copy-Primary Multiply (BGL specific).
Floating Convert from Integer Doubleword.
Condition Register AND with Complement.
Load Floating-Point Single Indexed.
Store Byte with Update Indexed.
FP2 Floating Parallel Subtract (BGL specific).
FP2 Floating Parallel Add (BGL specific).
Rotate Left Doubleword Immediate then Mask Insert.
Branch Conditional Link Register.
Store Floating-Point Single with Update Indexed.
Load Floating-Point Double Indexed.
FP2 Floating Parallel Reciprocal Estimate (BGL specific).
Move to Special-Purpose Register.
Rotate Left Doubleword Immediate then Clear.
Subtract from Minus One Extended.
Subtract from Immediate Carrying.
Shift Right Algebraic Doubleword Immediate.
Floating Round to Single Precision.
Floating Reciprocal Square Root Estimate (optional).
Floating-Point Square Root (optional).
Floating Negative Multiply-Add Single.
Floating Negative Multiply-Subtract Single.
Load Floating-Point Single with Update Indexed.
Main namespace for the ROSE library.
Store Word Byte-Reversed Indexed.
Load Half Algebraic with Update Indexed.
Floating Reciprocal Estimate Single (optional).
Store Floating-Point Single Indexed.
Move to Segment Register Indirect.
Move to Machine State Register.
PowerpcInstructionKind
PowerPC instruction types.
Load Half Algebraic with Update.
Floating Negative Multiply-Subtract Single.
Move to Condition Register from FPSCR.
Floating Reciprocal Square Root Estimate (optional).
Move to Machine State Register.
Floating Reciprocal Square Root Estimate (optional).
Load Half Byte-Reversed Indexed.
Rotate Left Doubleword Immediate then Mask Insert.
Subtract from Minus One Extended.
Load Half and Zero with Update.
Load Floating-Point Double with Update.
Rotate Left Word then AND with Mask.
Floating-Point Square Root (optional).
Rotate Left Doubleword then Clear Right.
Move Condition Register Field.
Floating-Point Register (0..31; 64 bits each).
Move to Condition Register Fields.
External Control out Word Indexed (opt.).
Move from Machine State Register.
Data Cache Block Set to Zero.
Condition Register Equivalent.
Floating Convert to Integer Word with Round to Zero.
Floating Negative Multiply-Subtract.
Load Word Byte-Reversed Indexed.
Move to Segment Register Indirect.
Floating Reciprocal Estimate Single (optional).
Load Half and Zero with Update Indexed.
Store Floating-Point Single with Update.
Load Word Algebraic with Update Indexed.
Floating Negative Multiply-Subtract.
Move to Condition Register from XER.
Special-purpose register (0..1023).
Load Floating-Point Double with Update Indexed.
Store Floating-Point Double Indexed.
Store Floating-Point Double with Update Indexed.
instruction address (pseudo) register.
Load Word and Reserve Indexed.
Rotate Left Word then AND with Mask.
Floating Convert to Integer Doubleword.
Store Doubleword Conditional Indexed.
Shift Right Algebraic Word Immediate.
Multiply High Doubleword Unsigned.
Load Doubleword with Update Indexed.
Floating point status and control register.
Floating Convert to Integer Doubleword.
Move from Condition Register.
Branch Conditional to Count Register.
PowerpcWordSize
PowerPC word size.
Floating Round to Single Precision.
Floating Convert from Integer Doubleword.
Store Floating-Point Double with Update.
Store Half Byte-Reverse Indexed.
Rotate Left Word Immediate then AND with Mask.
Floating Negative Absolute Value.
Floating-Point Square Root (optional).
Rotate Left Doubleword Immediate then Clear Left.
Instruction Cache Block Invalidate.
Floating Convert to Integer Doubleword with Round Toward Zero.
fixed-point exception register.
Branch Conditional Link Register.
Floating Multiply-Subtract Single.
Rotate Left Word Immediate then Mask Insert.
Store Doubleword with Update.
Floating Negative Multiply-Add.
Rotate Left Word Immediate then Mask Insert.
FP2 Floating Parallel Reciprocal Square Root Estimate (BGL specific).
Rotate Left Doubleword Immediate then Clear.
Floating Convert to Integer Doubleword with Round Toward Zero.
Shift Right Algebraic Doubleword.
Store Half with Update Indexed.
PowerpcTimeBaseRegister
PowerPC time base registers.
PowerpcConditionRegisterAccessGranularity
PowerPC condition register access granularity.
Floating Convert to Integer Word with Round to Zero.
External Control in Word Indexed (opt.).
Store Word with Update Indexed.
FP2 Floating Cross Multiply (BGL specific).
Load Doubleword and Reserve Indexed.
Condition Register OR with Complement.
Load Floating-Point Single with Update.
PowerpcRegisterClass
PowerPC register classes.
Shift Right Algebraic Doubleword Immediate.
Load Word and Zero with Update Indexed.
Rotate Left Word Immediate then AND with Mask.
Translation Look-aside Buffer Invalidate All (optional).
Store Doubleword with Update Indexed.
FP2 Floating Cross Copy-Secondary Multiply (BGL specific).
Translation Look-aside Buffer Invalidate Entry (optional).
Load Byte and Zero with Update Indexed.
Floating Reciprocal Square Root Estimate (optional).