Description
Architecture-specific information for x86-64, x86_64, x64, amd64, Intel 64.
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, announced in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mode.
With 64-bit mode and the new paging mode, it supports vastly larger amounts of virtual memory and physical memory than was possible on its 32-bit predecessors, allowing programs to store larger amounts of data in memory. x86-64 also expands general-purpose registers to 64-bit, and expands the number of them from 8 (some of which had limited or fixed functionality, e.g. for stack management) to 16 (fully general), and provides numerous other enhancements. Floating-point arithmetic is supported via mandatory SSE2-like instructions, and x87/MMX style registers are generally not used (but still available even in 64-bit mode); instead, a set of 16 vector registers, 128 bits each, is used. (Each register can store one or two double-precision numbers or one to four single-precision numbers, or various integer formats.) In 64-bit mode, instructions are modified to support 64-bit operands and 64-bit addressing mode.
The compatibility mode defined in the architecture allows 16-bit and 32-bit user applications to run unmodified, coexisting with 64-bit applications if the 64-bit operating system supports them. As the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, these older executables can run with little or no performance penalty, while newer or modified applications can take advantage of new features of the processor design to achieve performance improvements. Also, a processor supporting x86-64 still powers on in real mode for full backward compatibility with the 8086, as x86 processors supporting protected mode have done since the 80286.
The original specification, created by AMD and released in 2000, has been implemented by AMD, Intel, and VIA. The AMD K8 microarchitecture, in the Opteron and Athlon 64 processors, was the first to implement it. This was the first significant addition to the x86 architecture designed by a company other than Intel. Intel was forced to follow suit and introduced a modified NetBurst family which was software-compatible with AMD's specification. VIA Technologies introduced x86-64 in their VIA Isaiah architecture, with the VIA Nano.
The x86-64 architecture was quickly adopted for desktop and laptop personal computers and servers which were commonly configured for 16GB of memory or more. It has effectively replaced the discontinued Intel Itanium architecture (formerly IA-64), which was originally intended to replace the x86 architecture. x86-64 and Itanium are not compatible on the native instruction set level, and operating systems and applications compiled for one architecture cannot be run on the other natively.
#include <Rose/BinaryAnalysis/Architecture/Amd64.h>
Public Types | |
| using | Ptr = Amd64Ptr |
 Public Types inherited from Rose::BinaryAnalysis::Architecture::X86 | |
| using | Ptr = X86Ptr |
| Public Types inherited from Rose::BinaryAnalysis::Architecture::Base | |
| using | Ptr = BasePtr |
| Reference counting pointer. | |
| using | ConstPtr = BaseConstPtr |
| Reference counting pointer to const object. | |
Public Member Functions | |
| Sawyer::Container::Interval< size_t > | bytesPerInstruction () const override |
| Valid sizes for encoded machine instructions. | |
| Alignment | instructionAlignment () const override |
| Alignment for encoded machine instructions. | |
| RegisterDictionary::Ptr | registerDictionary () const override |
| Property: Register dictionary. | |
| bool | matchesHeader (SgAsmGenericHeader *) const override |
| Tests whether this architecture matches a file header. | |
| const CallingConvention::Dictionary & | callingConventions () const override |
| Property: Calling convention definitions. | |
| Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::X86 | |
| Sawyer::Container::Interval< size_t > | bytesPerInstruction () const override |
| Valid sizes for encoded machine instructions. | |
| Alignment | instructionAlignment () const override |
| Alignment for encoded machine instructions. | |
| std::string | instructionMnemonic (const SgAsmInstruction *) const override |
| Mnemonic for an instruction. | |
| bool | terminatesBasicBlock (SgAsmInstruction *) const override |
| Determines whether the specified instruction normally terminates a basic block. | |
| bool | isUnknown (const SgAsmInstruction *) const override |
| Returns true if the instruction is the special "unknown" instruction. | |
| bool | isFunctionCallFast (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override |
| Returns true if the specified basic block looks like a function call. | |
| bool | isFunctionCallSlow (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override |
| Returns true if the specified basic block looks like a function call. | |
| bool | isFunctionReturnFast (const std::vector< SgAsmInstruction * > &) const override |
| Returns true if the specified basic block looks like a function return. | |
| Sawyer::Optional< rose_addr_t > | branchTarget (SgAsmInstruction *) const override |
| Obtains the virtual address for a branching instruction. | |
| AddressSet | getSuccessors (SgAsmInstruction *, bool &complete) const override |
| Control flow successors for a single instruction. | |
| AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete, const MemoryMapPtr &initial_memory=MemoryMapPtr()) const override |
| Control flow successors for a basic block. | |
| Disassembler::BasePtr | newInstructionDecoder () const override |
| Construct and return a new instruction decoder. | |
| Unparser::BasePtr | newUnparser () const override |
| Construct and return a new instruction unparser. | |
| virtual InstructionSemantics::BaseSemantics::DispatcherPtr | newInstructionDispatcher (const InstructionSemantics::BaseSemantics::RiscOperatorsPtr &) const override |
| Construct and return a new instruction dispatcher. | |
| virtual std::vector< Partitioner2::FunctionPrologueMatcherPtr > | functionPrologueMatchers (const Partitioner2::EnginePtr &) const override |
| Instruction patterns matching function prologues. | |
| virtual std::vector< Partitioner2::BasicBlockCallbackPtr > | basicBlockCreationHooks (const Partitioner2::EnginePtr &) const override |
| Architecture-specific basic block callbacks for partitioning. | |
| Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base | |
| const std::string & | name () const |
| Property: Architecture definition name. | |
| ByteOrder::Endianness | byteOrder () const |
| Property: Byte order for memory. | |
| virtual RegisterDictionaryPtr | interruptDictionary () const |
| Property: Interrupt dictionary. | |
| virtual bool | matchesName (const std::string &) const |
| Tests whether this architecture matches a name. | |
| bool | instructionsCanOverlap () const |
| Whether instructions can overlap in memory. | |
| virtual std::string | toString (const SgAsmExpression *) const |
| Unparse an expression to a string. | |
| virtual std::string | instructionDescription (const SgAsmInstruction *) const |
| Description for an instruction. | |
| virtual bool | isControlTransfer (const SgAsmInstruction *) const |
| Returns true if the specified instruction is a control transfer instruction. | |
| const Sawyer::Optional< size_t > & | registrationId () const |
| Property: Registration identification number. | |
| void | registrationId (const Sawyer::Optional< size_t > &) |
| Property: Registration identification number. | |
| size_t | bytesPerWord () const |
| Property: Word size. | |
| size_t | bitsPerWord () const |
| Property: Word size. | |
| virtual Unparser::BasePtr | newInstructionUnparser () const |
| Construct and return a new instruction unparser. | |
| virtual std::string | toString (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual std::string | toStringNoAddr (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual bool | isFunctionReturnSlow (const std::vector< SgAsmInstruction * > &) const |
| Returns true if the specified basic block looks like a function return. | |
| AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete) const |
| Control flow successors for a basic block. | |
Static Public Member Functions | |
| static Ptr | instance () |
| Allocating constructor. | |
Protected Member Functions | |
| CallingConvention::DefinitionPtr | cc_sysv () const |
| Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::X86 | |
| X86 (const std::string &name, size_t bytesPerWord) | |
| CallingConvention::Definition::Ptr | cc_cdecl (size_t bitsPerWord) const |
| CallingConvention::Definition::Ptr | cc_stdcall (size_t bitsPerWord) const |
| CallingConvention::Definition::Ptr | cc_fastcall (size_t bitsPerWord) const |
| Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base | |
| Base (const std::string &name, size_t bytesPerWord, ByteOrder::Endianness byteOrder) | |
| Ptr | ptr () |
| ConstPtr | constPtr () const |
| virtual Unparser::BasePtr | insnUnparser () const |
Additional Inherited Members | |
| Protected Attributes inherited from Rose::BinaryAnalysis::Architecture::Base | |
| Sawyer::Cached< RegisterDictionaryPtr > | registerDictionary_ |
| Sawyer::Cached< RegisterDictionaryPtr > | interruptDictionary_ |
| Sawyer::Cached< CallingConvention::Dictionary > | callingConventions_ |
| Sawyer::Cached< Unparser::Base::Ptr > | insnToString_ |
| Sawyer::Cached< Unparser::Base::Ptr > | insnToStringNoAddr_ |
Member Typedef Documentation
◆ Ptr
| using Rose::BinaryAnalysis::Architecture::Amd64::Ptr = Amd64Ptr |
Member Function Documentation
◆ bytesPerInstruction()
|
overridevirtual |
Valid sizes for encoded machine instructions.
Returns the range of valid sizes for encoded machine instructions. For instance, an x86 instruction can be from one to 15 bytes in length, but a PowerPC PPC32 instruction is always exactly 4 bytes.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ instructionAlignment()
|
overridevirtual |
Alignment for encoded machine instructions.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ registerDictionary()
|
overridevirtual |
Property: Register dictionary.
The register dictionary defines a mapping between register names and register descriptors (RegisterDescriptor), and thus how the registers map into hardware.
Since dictionaries are generally not modified, it is permissible for this function to return the same dictionary every time it's called. The dictionary can be constructed on the first call.
Thread safety: Thread safe.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ matchesHeader()
|
overridevirtual |
Tests whether this architecture matches a file header.
Returns true if this architecture matches the specified file header, and false otherwise.
The default implementation always returns false.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
◆ callingConventions()
|
overridevirtual |
Property: Calling convention definitions.
Returns a list of calling convention definitions used by this architecture. Since definitions are generally not modified, it is permissible for this function to return the same definitions every time it's called. The list can be constructed on the first call.
The default implementation returns an empty list.
Thread safety: Thread safe.
Reimplemented from Rose::BinaryAnalysis::Architecture::X86.
The documentation for this class was generated from the following file:
