Description
Architecture-specific information for Intel 8086.
The 8086 (also called iAPX 86) is a 16-bit microprocessor chip designed by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088, released July 1, 1979, is a slightly modified chip with an external 8-bit data bus (allowing the use of cheaper and fewer supporting ICs), and is notable as the processor used in the original IBM PC design.
The 8086 gave rise to the x86 architecture, which eventually became Intel's most successful line of processors. On June 5, 2018, Intel released a limited-edition CPU celebrating the 40th anniversary of the Intel 8086, called the Intel Core i7-8086K.
Definition at line 19 of file Intel8086.h.
#include <Rose/BinaryAnalysis/Architecture/Intel8086.h>
Inheritance diagram for Rose::BinaryAnalysis::Architecture::Intel8086:
Collaboration diagram for Rose::BinaryAnalysis::Architecture::Intel8086:
Public Types | |
| using | Ptr = Intel8086Ptr |
 Public Types inherited from Rose::BinaryAnalysis::Architecture::X86 | |
| using | Ptr = X86Ptr |
| Public Types inherited from Rose::BinaryAnalysis::Architecture::Base | |
| using | Ptr = BasePtr |
| Reference counting pointer. | |
| using | ConstPtr = BaseConstPtr |
| Reference counting pointer to const object. | |
Public Member Functions | |
| RegisterDictionary::Ptr | registerDictionary () const override |
| Property: Register dictionary. | |
| bool | matchesHeader (SgAsmGenericHeader *) const override |
| Tests whether this architecture matches a file header. | |
| Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::X86 | |
| virtual const CallingConvention::Dictionary & | callingConventions () const override |
| Property: Calling convention definitions. | |
| Sawyer::Container::Interval< size_t > | bytesPerInstruction () const override |
| Valid sizes for encoded machine instructions. | |
| Alignment | instructionAlignment () const override |
| Alignment for encoded machine instructions. | |
| std::string | instructionMnemonic (const SgAsmInstruction *) const override |
| Mnemonic for an instruction. | |
| bool | terminatesBasicBlock (SgAsmInstruction *) const override |
| Determines whether the specified instruction normally terminates a basic block. | |
| bool | isUnknown (const SgAsmInstruction *) const override |
| Returns true if the instruction is the special "unknown" instruction. | |
| bool | isFunctionCallFast (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override |
| Returns true if the specified basic block looks like a function call. | |
| bool | isFunctionCallSlow (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override |
| Returns true if the specified basic block looks like a function call. | |
| bool | isFunctionReturnFast (const std::vector< SgAsmInstruction * > &) const override |
| Returns true if the specified basic block looks like a function return. | |
| Sawyer::Optional< rose_addr_t > | branchTarget (SgAsmInstruction *) const override |
| Obtains the virtual address for a branching instruction. | |
| AddressSet | getSuccessors (SgAsmInstruction *, bool &complete) const override |
| Control flow successors for a single instruction. | |
| AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete, const MemoryMapPtr &initial_memory=MemoryMapPtr()) const override |
| Control flow successors for a basic block. | |
| Disassembler::BasePtr | newInstructionDecoder () const override |
| Construct and return a new instruction decoder. | |
| Unparser::BasePtr | newUnparser () const override |
| Construct and return a new instruction unparser. | |
| virtual InstructionSemantics::BaseSemantics::DispatcherPtr | newInstructionDispatcher (const InstructionSemantics::BaseSemantics::RiscOperatorsPtr &) const override |
| Construct and return a new instruction dispatcher. | |
| virtual std::vector< Partitioner2::FunctionPrologueMatcherPtr > | functionPrologueMatchers (const Partitioner2::EnginePtr &) const override |
| Instruction patterns matching function prologues. | |
| virtual std::vector< Partitioner2::BasicBlockCallbackPtr > | basicBlockCreationHooks (const Partitioner2::EnginePtr &) const override |
| Architecture-specific basic block callbacks for partitioning. | |
| Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base | |
| const std::string & | name () const |
| Property: Architecture definition name. | |
| ByteOrder::Endianness | byteOrder () const |
| Property: Byte order for memory. | |
| virtual RegisterDictionaryPtr | interruptDictionary () const |
| Property: Interrupt dictionary. | |
| virtual bool | matchesName (const std::string &) const |
| Tests whether this architecture matches a name. | |
| bool | instructionsCanOverlap () const |
| Whether instructions can overlap in memory. | |
| virtual std::string | instructionDescription (const SgAsmInstruction *) const |
| Description for an instruction. | |
| const Sawyer::Optional< size_t > & | registrationId () const |
| Property: Registration identification number. | |
| void | registrationId (const Sawyer::Optional< size_t > &) |
| Property: Registration identification number. | |
| size_t | bytesPerWord () const |
| Property: Word size. | |
| size_t | bitsPerWord () const |
| Property: Word size. | |
| virtual std::string | toString (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual std::string | toStringNoAddr (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual bool | isFunctionReturnSlow (const std::vector< SgAsmInstruction * > &) const |
| Returns true if the specified basic block looks like a function return. | |
| AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete) const |
| Control flow successors for a basic block. | |
Static Public Member Functions | |
| static Ptr | instance () |
| Allocating constructor. | |
Additional Inherited Members | |
| Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::X86 | |
| X86 (const std::string &name, size_t bytesPerWord) | |
| CallingConvention::Definition::Ptr | cc_cdecl (size_t bitsPerWord) const |
| CallingConvention::Definition::Ptr | cc_stdcall (size_t bitsPerWord) const |
| CallingConvention::Definition::Ptr | cc_fastcall (size_t bitsPerWord) const |
| Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base | |
| Base (const std::string &name, size_t bytesPerWord, ByteOrder::Endianness byteOrder) | |
| Ptr | ptr () |
| ConstPtr | constPtr () const |
| Protected Attributes inherited from Rose::BinaryAnalysis::Architecture::Base | |
| Sawyer::Cached< RegisterDictionaryPtr > | registerDictionary_ |
| Sawyer::Cached< RegisterDictionaryPtr > | interruptDictionary_ |
| Sawyer::Cached< CallingConvention::Dictionary > | callingConventions_ |
| Sawyer::Cached< Unparser::Base::Ptr > | insnToString_ |
| Sawyer::Cached< Unparser::Base::Ptr > | insnToStringNoAddr_ |
Member Typedef Documentation
◆ Ptr
| using Rose::BinaryAnalysis::Architecture::Intel8086::Ptr = Intel8086Ptr |
Definition at line 21 of file Intel8086.h.
Member Function Documentation
◆ registerDictionary()
|
overridevirtual |
Property: Register dictionary.
The register dictionary defines a mapping between register names and register descriptors (RegisterDescriptor), and thus how the registers map into hardware.
Since dictionaries are generally not modified, it is permissible for this function to return the same dictionary every time it's called. The dictionary can be constructed on the first call.
Thread safety: Thread safe.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ matchesHeader()
|
overridevirtual |
Tests whether this architecture matches a file header.
Returns true if this architecture matches the specified file header, and false otherwise.
The default implementation always returns false.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
The documentation for this class was generated from the following file:
