ROSE 0.11.145.147
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Rose::BinaryAnalysis::Architecture::IntelPentium Class Reference

Description

Architecture-specific information for Intel Pentium.

The Pentium (also referred to as P5, its microarchitecture, or i586) is a fifth generation, 32-bit x86 microprocessor that was introduced by Intel on March 22, 1993, as the very first CPU in the Pentium brand. It was instruction set compatible with the 80486 but was a new and very different microarchitecture design from previous iterations. The P5 Pentium was the first superscalar x86 microarchitecture and the world's first superscalar microprocessor to be in mass production—meaning it generally executes at least 2 instructions per clock mainly because of a design-first dual integer pipeline design previously thought impossible to implement on a CISC microarchitecture. Additional features include a faster floating-point unit, wider data bus, separate code and data caches, and many other techniques and features to enhance performance and support security, encryption, and multiprocessing, for workstations and servers when compared to the next best previous industry standard processor implementation before it, the Intel 80486.

Considered the fifth main generation in the 8086 compatible line of processors, its implementation and microarchitecture was called P5. As with all new processors from Intel since the Pentium, some new instructions were added to enhance performance for specific types of workloads.

The Pentium was the first Intel x86 to build in robust hardware support for multiprocessing similar to that of large IBM mainframe computers. Intel worked closely with IBM to define this ability and then Intel designed it into the P5 microarchitecture. This new ability was absent in prior x86 generations and x86 copies from competitors.

Definition at line 30 of file IntelPentium.h.

#include <Rose/BinaryAnalysis/Architecture/IntelPentium.h>

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Public Types

using Ptr = IntelPentiumPtr
 
- Public Types inherited from Rose::BinaryAnalysis::Architecture::X86
using Ptr = X86Ptr
 
- Public Types inherited from Rose::BinaryAnalysis::Architecture::Base
using Ptr = BasePtr
 Reference counting pointer.
 
using ConstPtr = BaseConstPtr
 Reference counting pointer to const object.
 

Public Member Functions

RegisterDictionary::Ptr registerDictionary () const override
 Property: Register dictionary.
 
bool matchesHeader (SgAsmGenericHeader *) const override
 Tests whether this architecture matches a file header.
 
- Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::X86
virtual const CallingConvention::DictionarycallingConventions () const override
 Property: Calling convention definitions.
 
Sawyer::Container::Interval< size_t > bytesPerInstruction () const override
 Valid sizes for encoded machine instructions.
 
Alignment instructionAlignment () const override
 Alignment for encoded machine instructions.
 
std::string instructionMnemonic (const SgAsmInstruction *) const override
 Mnemonic for an instruction.
 
bool terminatesBasicBlock (SgAsmInstruction *) const override
 Determines whether the specified instruction normally terminates a basic block.
 
bool isUnknown (const SgAsmInstruction *) const override
 Returns true if the instruction is the special "unknown" instruction.
 
bool isFunctionCallFast (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override
 Returns true if the specified basic block looks like a function call.
 
bool isFunctionCallSlow (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override
 Returns true if the specified basic block looks like a function call.
 
bool isFunctionReturnFast (const std::vector< SgAsmInstruction * > &) const override
 Returns true if the specified basic block looks like a function return.
 
Sawyer::Optional< rose_addr_t > branchTarget (SgAsmInstruction *) const override
 Obtains the virtual address for a branching instruction.
 
AddressSet getSuccessors (SgAsmInstruction *, bool &complete) const override
 Control flow successors for a single instruction.
 
AddressSet getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete, const MemoryMapPtr &initial_memory=MemoryMapPtr()) const override
 Control flow successors for a basic block.
 
Disassembler::BasePtr newInstructionDecoder () const override
 Construct and return a new instruction decoder.
 
Unparser::BasePtr newUnparser () const override
 Construct and return a new instruction unparser.
 
virtual InstructionSemantics::BaseSemantics::DispatcherPtr newInstructionDispatcher (const InstructionSemantics::BaseSemantics::RiscOperatorsPtr &) const override
 Construct and return a new instruction dispatcher.
 
virtual std::vector< Partitioner2::FunctionPrologueMatcherPtrfunctionPrologueMatchers (const Partitioner2::EnginePtr &) const override
 Instruction patterns matching function prologues.
 
virtual std::vector< Partitioner2::BasicBlockCallbackPtrbasicBlockCreationHooks (const Partitioner2::EnginePtr &) const override
 Architecture-specific basic block callbacks for partitioning.
 
- Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base
const std::string & name () const
 Property: Architecture definition name.
 
ByteOrder::Endianness byteOrder () const
 Property: Byte order for memory.
 
virtual RegisterDictionaryPtr interruptDictionary () const
 Property: Interrupt dictionary.
 
virtual bool matchesName (const std::string &) const
 Tests whether this architecture matches a name.
 
bool instructionsCanOverlap () const
 Whether instructions can overlap in memory.
 
virtual std::string instructionDescription (const SgAsmInstruction *) const
 Description for an instruction.
 
const Sawyer::Optional< size_t > & registrationId () const
 Property: Registration identification number.
 
void registrationId (const Sawyer::Optional< size_t > &)
 Property: Registration identification number.
 
size_t bytesPerWord () const
 Property: Word size.
 
size_t bitsPerWord () const
 Property: Word size.
 
virtual std::string toString (const SgAsmInstruction *) const
 Unparse an instruction to a string.
 
virtual std::string toStringNoAddr (const SgAsmInstruction *) const
 Unparse an instruction to a string.
 
virtual bool isFunctionReturnSlow (const std::vector< SgAsmInstruction * > &) const
 Returns true if the specified basic block looks like a function return.
 
AddressSet getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete) const
 Control flow successors for a basic block.
 

Static Public Member Functions

static Ptr instance ()
 Allocating constructor.
 

Additional Inherited Members

- Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::X86
 X86 (const std::string &name, size_t bytesPerWord)
 
CallingConvention::Definition::Ptr cc_cdecl (size_t bitsPerWord) const
 
CallingConvention::Definition::Ptr cc_stdcall (size_t bitsPerWord) const
 
CallingConvention::Definition::Ptr cc_fastcall (size_t bitsPerWord) const
 
- Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base
 Base (const std::string &name, size_t bytesPerWord, ByteOrder::Endianness byteOrder)
 
Ptr ptr ()
 
ConstPtr constPtr () const
 
- Protected Attributes inherited from Rose::BinaryAnalysis::Architecture::Base
Sawyer::Cached< RegisterDictionaryPtrregisterDictionary_
 
Sawyer::Cached< RegisterDictionaryPtrinterruptDictionary_
 
Sawyer::Cached< CallingConvention::DictionarycallingConventions_
 
Sawyer::Cached< Unparser::Base::PtrinsnToString_
 
Sawyer::Cached< Unparser::Base::PtrinsnToStringNoAddr_
 

Member Typedef Documentation

◆ Ptr

using Rose::BinaryAnalysis::Architecture::IntelPentium::Ptr = IntelPentiumPtr

Definition at line 32 of file IntelPentium.h.

Member Function Documentation

◆ registerDictionary()

RegisterDictionary::Ptr Rose::BinaryAnalysis::Architecture::IntelPentium::registerDictionary ( ) const
overridevirtual

Property: Register dictionary.

The register dictionary defines a mapping between register names and register descriptors (RegisterDescriptor), and thus how the registers map into hardware.

Since dictionaries are generally not modified, it is permissible for this function to return the same dictionary every time it's called. The dictionary can be constructed on the first call.

Thread safety: Thread safe.

Implements Rose::BinaryAnalysis::Architecture::Base.

◆ matchesHeader()

bool Rose::BinaryAnalysis::Architecture::IntelPentium::matchesHeader ( SgAsmGenericHeader ) const
overridevirtual

Tests whether this architecture matches a file header.

Returns true if this architecture matches the specified file header, and false otherwise.

The default implementation always returns false.

Reimplemented from Rose::BinaryAnalysis::Architecture::Base.


The documentation for this class was generated from the following file: