2 #ifndef ROSE_BinaryAnalysis_DisassemblerPowerpc_H
3 #define ROSE_BinaryAnalysis_DisassemblerPowerpc_H
4 #include <featureTests.h>
5 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
6 #include <Rose/BinaryAnalysis/Disassembler.h>
8 #include "integerOps.h"
9 #include "SageBuilderAsm.h"
12 namespace BinaryAnalysis {
20 State(): ip(0), insn(0) {}
24 ByteOrder::Endianness sex_;
29 : wordSize_(wordSize), sex_(sex) {
46 class ExceptionPowerpc:
public Exception {
48 ExceptionPowerpc(
const std::string &mesg,
const State &state,
size_t bit=0)
52 bytes.push_back((state.insn>>24) & 0xff);
53 bytes.push_back((state.insn>>16) & 0xff);
54 bytes.push_back((state.insn>>8) & 0xff);
55 bytes.push_back(state.insn & 0xff);
56 ASSERT_require(bit<=32);
57 this->bit = 8*(4-(bit/8)) + bit%8;
77 template <
size_t First,
size_t Last> uint64_t fld(State&)
const;
80 bool AA(State &state)
const {
81 return fld<30, 30>(state);
92 uint64_t BD(State &state)
const {
93 return IntegerOps::signExtend<16, 64>((uint64_t)state.insn & 0xfffc);
113 return SageBuilderAsm::buildValueU8(fld<19, 20>(state));
121 return SageBuilderAsm::buildValueU8(fld<6, 10>(state));
131 return SageBuilderAsm::buildValueU32(IntegerOps::signExtend<16, 32>((uint64_t)fld<16, 31>(state)));
133 return SageBuilderAsm::buildValueU64(IntegerOps::signExtend<16, 64>((uint64_t)fld<16, 31>(state)));
135 ASSERT_not_reachable(
"invalid word size");
141 return SageBuilderAsm::buildValueU32(IntegerOps::signExtend<16, 32>((uint64_t)fld<16, 31>(state) & 0xfffc));
143 return SageBuilderAsm::buildValueU64(IntegerOps::signExtend<16, 64>((uint64_t)fld<16, 31>(state) & 0xfffc));
145 ASSERT_not_reachable(
"invalid word size");
149 return SageBuilderAsm::buildValueU8(fld<7, 14>(state));
173 return SageBuilderAsm::buildValueU8(fld<12, 19>(state));
177 return SageBuilderAsm::buildValueU8(fld<10, 10>(state));
181 return SageBuilderAsm::buildValueU8(fld<15, 15>(state));
184 uint8_t L_sync(State &state)
const {
185 return fld<9, 10>(state);
189 return SageBuilderAsm::buildValueU8(fld<20, 26>(state));
192 uint64_t LI(State &state)
const {
193 return IntegerOps::signExtend<26, 64>(uint64_t(fld<6, 29>(state) * 4));
196 bool LK(State &state)
const {
197 return fld<31, 31>(state);
201 return SageBuilderAsm::buildValueU8(fld<21, 25>(state));
205 return SageBuilderAsm::buildValueU8(fld<26, 30>(state));
209 return SageBuilderAsm::buildValueU8(fld<21, 25>(state) + 32 * fld<26, 26>(state));
213 return SageBuilderAsm::buildValueU8(fld<21, 25>(state) + 32 * fld<26, 26>(state));
217 return SageBuilderAsm::buildValueU8(fld<16, 20>(state) == 0 ? 32 : fld<16, 20>(state));
220 bool OE(State &state)
const {
221 return fld<21, 21>(state);
229 return fld<11, 15>(state) == 0 ? (
SgAsmExpression*)SageBuilderAsm::buildValueU8(0) : RA(state);
236 bool Rc(State &state)
const {
237 return fld<31, 31>(state);
249 return SageBuilderAsm::buildValueU8(fld<16, 20>(state));
253 return SageBuilderAsm::buildValueU8(fld<16, 20>(state) + fld<30, 30>(state) * 32);
273 return SageBuilderAsm::buildValueU8(fld<9, 10>(state));
277 return SageBuilderAsm::buildValueU8(fld<6, 10>(state));
281 return SageBuilderAsm::buildValueU8(fld<16, 19>(state));
287 return SageBuilderAsm::buildValueU32(fld<16, 31>(state));
289 return SageBuilderAsm::buildValueU64(fld<16, 31>(state));
291 ASSERT_not_reachable(
"invalid word size");
295 return SageBuilderAsm::buildMemoryReferenceExpression(SageBuilderAsm::buildAddExpression(RA_or_zero(state), D(state)), NULL, t);
299 return SageBuilderAsm::buildMemoryReferenceExpression(SageBuilderAsm::buildAddExpression(RA_or_zero(state), DS(state)), NULL, t);
303 return SageBuilderAsm::buildMemoryReferenceExpression(RA_or_zero(state), NULL, t);
307 return SageBuilderAsm::buildMemoryReferenceExpression(SageBuilderAsm::buildAddExpression(RA_or_zero(state), RB(state)),
312 if (fld<11, 15>(state) == 0)
313 throw ExceptionPowerpc(
"bits 11-15 must be nonzero", state);
314 return SageBuilderAsm::buildMemoryReferenceExpression(SageBuilderAsm::buildAddExpression(RA(state), D(state)), NULL, t);
318 if (fld<11, 15>(state) == 0)
319 throw ExceptionPowerpc(
"bits 11-15 must be nonzero", state);
320 return SageBuilderAsm::buildMemoryReferenceExpression(SageBuilderAsm::buildAddExpression(RA(state), RB(state)), NULL, t);
348 void startInstruction(State &state, rose_addr_t start_va, uint32_t c)
const {
Base class for references to a machine register.
Condition Register (only particular fields or bits may be used).
Base class for machine instructions.
Time base register (0..1023).
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &map, rose_addr_t start_va, AddressSet *successors=NULL)
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
virtual Unparser::BasePtr unparser() const
Unparser.
Main namespace for the ROSE library.
DisassemblerPowerpc(PowerpcWordSize wordSize, ByteOrder::Endianness sex)
Constructor for 32- or 64-bit disassembler.
PowerpcInstructionKind
PowerPC instruction types.
virtual bool canDisassemble(SgAsmGenericHeader *) const
Predicate determining the suitability of a disassembler for a specific file header.
Reference to memory locations.
Base class for integer values.
Floating-Point Register (0..31; 64 bits each).
Represents one PowerPC machine instruction.
Special-purpose register (0..1023).
Base class for expressions.
Whole CR (or unknown or not using a CR).
Floating point status and control register.
Base class for binary types.
PowerpcWordSize
PowerPC word size.
General Purpose Register (0..31).
PowerpcConditionRegisterAccessGranularity
PowerPC condition register access granularity.
Base class for all ROSE exceptions.
virtual DisassemblerPowerpc * clone() const
Creates a new copy of a disassembler.
Virtual base class for instruction disassemblers.
Disassembler for the PowerPC architecture.
PowerpcRegisterClass
PowerPC register classes.
virtual SgAsmInstruction * makeUnknownInstruction(const Exception &)
Makes an unknown instruction from an exception.