2 #ifndef ROSE_BinaryAnalysis_DisassemblerX86_H
3 #define ROSE_BinaryAnalysis_DisassemblerX86_H
4 #include <featureTests.h>
5 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
6 #include <Rose/BinaryAnalysis/Disassembler.h>
8 #include <Rose/BinaryAnalysis/InstructionEnumsX86.h>
9 #include "Cxx_GrammarSerialization.h"
11 #include <boost/serialization/access.hpp>
12 #include <boost/serialization/base_object.hpp>
13 #include <boost/serialization/export.hpp>
14 #include <boost/serialization/split_member.hpp>
17 namespace BinaryAnalysis {
29 SgUnsignedCharList insnbuf;
35 bool branchPredictionEnabled;
36 bool rexPresent, rexW, rexR, rexX, rexB;
38 bool operandSizeOverride;
39 bool addressSizeOverride;
49 bool isUnconditionalJump;
52 : ip(0), insnbufat(0), segOverride(x86_segreg_none), branchPrediction(x86_branch_prediction_none),
53 branchPredictionEnabled(
false), rexPresent(
false), rexW(
false), rexR(
false), rexX(
false), rexB(
false),
54 sizeMustBe64Bit(
false), operandSizeOverride(
false), addressSizeOverride(
false), lock(
false),
55 repeatPrefix(
x86_repeat_none), modregrmByteSet(
false), modregrmByte(0), modeField(0), regField(0),
56 rmField(0), modrm(NULL), reg(NULL), isUnconditionalJump(
false) {}
62 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
64 friend class boost::serialization::access;
67 void serialize_common(S &s,
const unsigned ) {
72 s & BOOST_SERIALIZATION_NVP(wordSize);
76 void save(S &s,
const unsigned version)
const {
77 serialize_common(s, version);
81 void load(S &s,
const unsigned version) {
82 serialize_common(s, version);
86 BOOST_SERIALIZATION_SPLIT_MEMBER();
96 : insnSize(x86_insnsize_none), wordSize(0) {}
100 : insnSize(x86_insnsize_none), wordSize(0) {
132 ExceptionX86(
const std::string &mesg,
const State &state)
134 ASSERT_require(state.insnbufat <= state.insnbuf.size());
135 if (state.insnbufat > 0)
136 bytes = SgUnsignedCharList(&state.insnbuf[0], &state.insnbuf[0] + state.insnbufat);
137 bit = 8 * state.insnbufat;
140 ExceptionX86(
const std::string &mesg,
const State &state,
size_t bit)
142 ASSERT_require(state.insnbufat <= state.insnbuf.size());
143 if (state.insnbufat > 0)
144 bytes = SgUnsignedCharList(&state.insnbuf[0], &state.insnbuf[0] + state.insnbufat);
151 rmLegacyByte, rmRexByte, rmWord, rmDWord, rmQWord, rmSegment, rmST, rmMM, rmXMM, rmControl, rmDebug, rmReturnNull
156 mmNone, mmF3, mm66, mmF2
168 uint8_t getByte(State &state)
const;
173 uint16_t getWord(State &state)
const;
178 uint32_t getDWord(State &state)
const;
183 uint64_t getQWord(State &state)
const;
199 RegisterMode effectiveOperandMode(State &state)
const {
200 return sizeToMode(effectiveOperandSize(state));
209 SgAsmType *effectiveOperandType(State &state)
const {
210 return sizeToType(effectiveOperandSize(state));
214 bool longMode()
const {
219 MMPrefix mmPrefix(State &state)
const;
222 void not64(State &state)
const {
224 throw ExceptionX86(
"not valid for 64-bit code", state);
229 void setRex(State &state, uint8_t prefix)
const;
247 SgAsmExpression *makeAddrSizeValue(State &state, int64_t val,
size_t bit_offset,
size_t bit_size)
const;
273 return makeRegister(state, fullRegisterNumber, effectiveOperandMode(state));
278 return makeRegister(state, registerNumber + (rexExtension ? 8 : 0), effectiveOperandMode(state));
304 void getModRegRM(State &state, RegisterMode regMode, RegisterMode rmMode,
SgAsmType *t,
SgAsmType *tForReg = NULL)
const;
311 void fillInModRM(State &state, RegisterMode rmMode,
SgAsmType *t)
const;
321 void requireMemory(State &state)
const {
322 if (!state.modregrmByteSet)
323 throw ExceptionX86(
"requires Mod/RM byte", state);
324 if (state.modeField == 3)
325 throw ExceptionX86(
"requires memory", state);
435 void init(
size_t wordsize);
437 #if 0 // is this ever used?
444 state.branchPredictionEnabled = state.branchPrediction != x86_branch_prediction_none;
450 void startInstruction(State &state, rose_addr_t start_va,
const uint8_t *buf,
size_t bufsz)
const {
452 state.insnbuf = SgUnsignedCharList(buf, buf+bufsz);
456 state.segOverride = x86_segreg_none;
457 state.branchPrediction = x86_branch_prediction_none;
458 state.branchPredictionEnabled =
false;
459 state.rexPresent = state.rexW = state.rexR = state.rexX = state.rexB =
false;
460 state.sizeMustBe64Bit =
false;
461 state.operandSizeOverride =
false;
462 state.addressSizeOverride =
false;
465 state.modregrmByteSet =
false;
466 state.modregrmByte = state.modeField = state.regField = state.rmField = 0;
467 state.modrm = state.reg = NULL;
468 state.isUnconditionalJump =
false;
479 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
virtual DisassemblerX86 * clone() const override
Creates a new copy of a disassembler.
virtual bool canDisassemble(SgAsmGenericHeader *) const override
Predicate determining the suitability of a disassembler for a specific file header.
Instruction is for a 64-bit architecture.
Base class for references to a machine register.
Base class for machine instructions.
X86BranchPrediction
Intel x86 branch prediction types.
Rose::BinaryAnalysis::X86InstructionSize get_baseSize() const
Property: An enum constant describing the base size of an x86 instruction.
Rose::BinaryAnalysis::X86BranchPrediction get_branchPrediction() const
Property: An enum constant describing branch prediction.
Rose::BinaryAnalysis::X86SegmentRegister get_segmentOverride() const
Property: The segment override register.
Main namespace for the ROSE library.
Reference to memory locations.
bool get_lockPrefix() const
Property: Whether the x86 lock prefix was present.
virtual SgAsmInstruction * makeUnknownInstruction(const Exception &) override
Makes an unknown instruction from an exception.
Represents one Intel x86 machine instruction.
virtual Unparser::BasePtr unparser() const override
Unparser.
Base class for expressions.
Base class for binary types.
Disassembler for the x86 architecture.
X86SegmentRegister
Intel x86 segment registers.
X86InstructionKind
List of all x86 instructions known to the ROSE disassembler/assembler.
rose_addr_t get_address() const
Property: Starting virtual address.
Base class for all ROSE exceptions.
Virtual base class for instruction disassemblers.
X86InstructionSize
Intel x86 instruction size constants.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &map, rose_addr_t start_va, AddressSet *successors=NULL) override
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
X86RepeatPrefix
Intel x86 instruction repeat prefix.