DisassemblerX86.h

/* Disassembly specific to the x86 architecture. */

#ifndef ROSE_DISASSEMBLER_X86_H
#define ROSE_DISASSEMBLER_X86_H

#include "Disassembler.h"
#ifdef ROSE_BUILD_BINARY_ANALYSIS_SUPPORT

#include "InstructionEnumsX86.h"
#include "Cxx_GrammarSerialization.h"

#include <boost/serialization/access.hpp>
#include <boost/serialization/base_object.hpp>
#include <boost/serialization/export.hpp>
#include <boost/serialization/split_member.hpp>

namespace Rose {
namespace BinaryAnalysis {

class DisassemblerX86: public Disassembler {
    /* Per-disassembler settings; see init() */
    X86InstructionSize insnSize;                    
    size_t wordSize;                                
    /* Per-instruction settings; see startInstruction() */
    struct State {
        uint64_t ip;                                
        SgUnsignedCharList insnbuf;                 
        size_t insnbufat;                           
        /* Temporary flags set by the instruction; initialized by startInstruction() */
        X86SegmentRegister segOverride;             
        X86BranchPrediction branchPrediction;       /*FIXME: this seems to set only to x86_branch_prediction_true [RPM 2009-06-16] */
        bool branchPredictionEnabled;
        bool rexPresent, rexW, rexR, rexX, rexB;    
        bool sizeMustBe64Bit;                       
        bool operandSizeOverride;                   
        bool addressSizeOverride;                   
        bool lock;                                  
        X86RepeatPrefix repeatPrefix;               
        bool modregrmByteSet;                       
        uint8_t modregrmByte;                       
        uint8_t modeField;                          
        uint8_t regField;                           
        uint8_t rmField;                            
        SgAsmExpression *modrm;                     
        SgAsmExpression *reg;                       
        bool isUnconditionalJump;                   
        State()
            : ip(0), insnbufat(0), segOverride(x86_segreg_none), branchPrediction(x86_branch_prediction_none),
              branchPredictionEnabled(false), rexPresent(false), rexW(false), rexR(false), rexX(false), rexB(false),
              sizeMustBe64Bit(false), operandSizeOverride(false), addressSizeOverride(false), lock(false),
              repeatPrefix(x86_repeat_none), modregrmByteSet(false), modregrmByte(0), modeField(0), rmField(0),
              modrm(NULL), reg(NULL), isUnconditionalJump(false) {}
    };

    // Serialization
#ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
private:
    friend class boost::serialization::access;

    template<class S>
    void serialize_common(S &s, const unsigned /*version*/) {
        // Most of the data members don't need to be saved because we'll only save/restore disassemblers that are between
        // instructions (we never save one while it's processing an instruction). Therefore, most of the data members can be
        // constructed in their initial state by a combination of default constructor and init().
        s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Disassembler);
        s & BOOST_SERIALIZATION_NVP(wordSize);
    }

    template<class S>
    void save(S &s, const unsigned version) const {
        serialize_common(s, version);
    }

    template<class S>
    void load(S &s, const unsigned version) {
        serialize_common(s, version);
        init(wordSize);
    }

    BOOST_SERIALIZATION_SPLIT_MEMBER();
#endif

    // Constructors

protected:
    // Default constructor for serialization
    DisassemblerX86()
        : insnSize(x86_insnsize_none), wordSize(0) {}

public:
    explicit DisassemblerX86(size_t wordsize)
        : insnSize(x86_insnsize_none), wordSize(0) {
        init(wordsize);
    }

    virtual ~DisassemblerX86() {}

    virtual DisassemblerX86 *clone() const ROSE_OVERRIDE { return new DisassemblerX86(*this); }

    // Public methods
public:
    virtual bool canDisassemble(SgAsmGenericHeader*) const ROSE_OVERRIDE;

    virtual Unparser::BasePtr unparser() const ROSE_OVERRIDE;

    virtual SgAsmInstruction *disassembleOne(const MemoryMap::Ptr &map, rose_addr_t start_va,
                                             AddressSet *successors=NULL) ROSE_OVERRIDE;

    virtual SgAsmInstruction *makeUnknownInstruction(const Exception&) ROSE_OVERRIDE;


    /*========================================================================================================================
     * Data types
     *========================================================================================================================*/
private:

    class ExceptionX86: public Exception {
    public:
        ExceptionX86(const std::string &mesg, const State &state)
            : Exception(mesg, state.ip) {
            ASSERT_require(state.insnbufat <= state.insnbuf.size());
            if (state.insnbufat > 0)
                bytes = SgUnsignedCharList(&state.insnbuf[0], &state.insnbuf[0] + state.insnbufat);
            bit = 8 * state.insnbufat;
        }

        ExceptionX86(const std::string &mesg, const State &state, size_t bit)
            : Exception(mesg, state.ip) {
            ASSERT_require(state.insnbufat <= state.insnbuf.size());
            if (state.insnbufat > 0)
                bytes = SgUnsignedCharList(&state.insnbuf[0], &state.insnbuf[0] + state.insnbufat);
            this->bit = bit;
        }
    };

    enum RegisterMode {
        rmLegacyByte, rmRexByte, rmWord, rmDWord, rmQWord, rmSegment, rmST, rmMM, rmXMM, rmControl, rmDebug, rmReturnNull
    };

    /* MMX registers? See mmPrefix method */
    enum MMPrefix {
        mmNone, mmF3, mm66, mmF2
    };


    /*========================================================================================================================
     * Methods for reading and writing bytes of the instruction.  These keep track of how much has been read or written.
     *========================================================================================================================*/
private:

    uint8_t getByte(State &state) const;

    uint16_t getWord(State &state) const;

    uint32_t getDWord(State &state) const;

    uint64_t getQWord(State &state) const;

    /*========================================================================================================================
     * Miscellaneous helper methods
     *========================================================================================================================*/
private:
    SgAsmExpression *currentDataSegment(State &state) const;

    X86InstructionSize effectiveAddressSize(State &state) const;

    RegisterMode effectiveOperandMode(State &state) const {
        return sizeToMode(effectiveOperandSize(state));
    }

    X86InstructionSize effectiveOperandSize(State &state) const;

    SgAsmType *effectiveOperandType(State &state) const {
        return sizeToType(effectiveOperandSize(state));
    }

    bool longMode() const {
        return insnSize == x86_insnsize_64;
    }

    /* FIXME: documentation? */
    MMPrefix mmPrefix(State &state) const;

    void not64(State &state) const {
        if (longMode())
            throw ExceptionX86("not valid for 64-bit code", state);
    }

    void setRex(State &state, uint8_t prefix) const;

    static RegisterMode sizeToMode(X86InstructionSize);

    static SgAsmType *sizeToType(X86InstructionSize s);



    /*========================================================================================================================
     * Methods that construct something. (Their names all start with "make".)
     *========================================================================================================================*/
private:

    SgAsmExpression *makeAddrSizeValue(State &state, int64_t val, size_t bit_offset, size_t bit_size) const;

    SgAsmX86Instruction *makeInstruction(State &state, X86InstructionKind kind, const std::string &mnemonic,
                                         SgAsmExpression *op1=NULL, SgAsmExpression *op2=NULL,
                                         SgAsmExpression *op3=NULL, SgAsmExpression *op4=NULL) const;

    SgAsmRegisterReferenceExpression *makeIP() const;

    /* FIXME: documentation? */
    SgAsmRegisterReferenceExpression *makeOperandRegisterByte(State &state, bool rexExtension, uint8_t registerNumber) const;

    /* FIXME: documentation? */
    SgAsmRegisterReferenceExpression *makeOperandRegisterFull(State &state, bool rexExtension, uint8_t registerNumber) const;

    SgAsmRegisterReferenceExpression *makeRegister(State &state, uint8_t fullRegisterNumber, RegisterMode,
                                                   SgAsmType *registerType=NULL) const;

    /* FIXME: documentation? */
    SgAsmRegisterReferenceExpression *makeRegisterEffective(State &state, uint8_t fullRegisterNumber) const {
        return makeRegister(state, fullRegisterNumber, effectiveOperandMode(state));
    }

    /* FIXME: documentation? */
    SgAsmRegisterReferenceExpression *makeRegisterEffective(State &state, bool rexExtension, uint8_t registerNumber) const {
        return makeRegister(state, registerNumber + (rexExtension ? 8 : 0), effectiveOperandMode(state));
    }

    SgAsmExpression *makeSegmentRegister(State &state, X86SegmentRegister so, bool insn64) const;



    /*========================================================================================================================
     * Methods for operating on the ModR/M byte.
     *========================================================================================================================*/
private:

    void getModRegRM(State &state, RegisterMode regMode, RegisterMode rmMode, SgAsmType *t, SgAsmType *tForReg = NULL) const;

    SgAsmMemoryReferenceExpression *decodeModrmMemory(State &state) const;

    void fillInModRM(State &state, RegisterMode rmMode, SgAsmType *t) const;

    SgAsmExpression *makeModrmNormal(State &state, RegisterMode, SgAsmType *mrType) const;

    SgAsmRegisterReferenceExpression *makeModrmRegister(State &state, RegisterMode, SgAsmType* mrType=NULL) const;

    void requireMemory(State &state) const {
        if (!state.modregrmByteSet)
            throw ExceptionX86("requires Mod/RM byte", state);
        if (state.modeField == 3)
            throw ExceptionX86("requires memory", state);
    }



    /*========================================================================================================================
     * Methods that construct an SgAsmExpression for an immediate operand.
     *========================================================================================================================*/
private:

    SgAsmExpression *getImmByte(State &state) const;
    SgAsmExpression *getImmWord(State &state) const;
    SgAsmExpression* getImmDWord(State &state) const;
    SgAsmExpression* getImmQWord(State &state) const;
    SgAsmExpression *getImmForAddr(State &state) const;
    SgAsmExpression *getImmIv(State &state) const;
    SgAsmExpression *getImmJz(State &state) const;
    SgAsmExpression *getImmByteAsIv(State &state) const;
    SgAsmExpression *getImmIzAsIv(State &state) const;
    SgAsmExpression *getImmJb(State &state) const;




    /*========================================================================================================================
     * Main disassembly functions, each generally containing a huge "switch" statement based on one of the opcode bytes.
     *========================================================================================================================*/
private:

    SgAsmX86Instruction *disassemble(State &state) const;

    SgAsmX86Instruction *decodeOpcode0F(State &state) const;

    SgAsmX86Instruction *decodeOpcode0F38(State &state) const;

    SgAsmX86Instruction *decodeX87InstructionD8(State &state) const;

    SgAsmX86Instruction *decodeX87InstructionD9(State &state) const;

    SgAsmX86Instruction *decodeX87InstructionDA(State &state) const;

    SgAsmX86Instruction *decodeX87InstructionDB(State &state) const;

    SgAsmX86Instruction *decodeX87InstructionDC(State &state) const;

    SgAsmX86Instruction *decodeX87InstructionDD(State &state) const;

    SgAsmX86Instruction *decodeX87InstructionDE(State &state) const;

    SgAsmX86Instruction *decodeX87InstructionDF(State &state) const;

    SgAsmX86Instruction *decodeGroup1(State &state, SgAsmExpression *imm) const;

    SgAsmX86Instruction *decodeGroup1a(State &state) const;

    SgAsmX86Instruction *decodeGroup2(State &state, SgAsmExpression *count) const;

    SgAsmX86Instruction *decodeGroup3(State &state, SgAsmExpression *immMaybe) const;

    SgAsmX86Instruction *decodeGroup4(State &state) const;

    SgAsmX86Instruction *decodeGroup5(State &state) const;

    SgAsmX86Instruction *decodeGroup6(State &state) const;

    SgAsmX86Instruction *decodeGroup7(State &state) const;

    SgAsmX86Instruction *decodeGroup8(State &state, SgAsmExpression *imm) const;

    SgAsmX86Instruction *decodeGroup11(State &state, SgAsmExpression *imm) const;

    SgAsmX86Instruction *decodeGroup15(State &state) const;

    SgAsmX86Instruction *decodeGroup16(State &state) const;

    SgAsmX86Instruction *decodeGroupP(State &state) const;



    /*========================================================================================================================
     * Supporting functions
     *========================================================================================================================*/
private:
    // Initialize instances of this class. Called by constructor.
    void init(size_t wordsize);

#if 0 // is this ever used?

    void startInstruction(State &state, SgAsmX86Instruction *insn) const {
        startInstruction(insn->get_address(), NULL, 0);
        insnSize = insn->get_baseSize();
        state.lock = insn->get_lockPrefix();
        state.branchPrediction = insn->get_branchPrediction();
        state.branchPredictionEnabled = state.branchPrediction != x86_branch_prediction_none;
        state.segOverride = insn->get_segmentOverride();
    }
#endif

    // Resets disassembler state to beginning of an instruction for disassembly.
    void startInstruction(State &state, rose_addr_t start_va, const uint8_t *buf, size_t bufsz) const {
        state.ip = start_va;
        state.insnbuf = SgUnsignedCharList(buf, buf+bufsz);
        state.insnbufat = 0;

        // Prefix flags
        state.segOverride = x86_segreg_none;
        state.branchPrediction = x86_branch_prediction_none;
        state.branchPredictionEnabled = false;
        state.rexPresent = state.rexW = state.rexR = state.rexX = state.rexB = false;
        state.sizeMustBe64Bit = false;
        state.operandSizeOverride = false;
        state.addressSizeOverride = false;
        state.lock = false;
        state.repeatPrefix = x86_repeat_none;
        state.modregrmByteSet = false;
        state.modregrmByte = state.modeField = state.regField = state.rmField = 0; /*arbitrary since modregrmByteSet is false*/
        state.modrm = state.reg = NULL;
        state.isUnconditionalJump = false;
    }

    // Add comments to any IP relative addition expressions. We're not constant folding these because it's sometimes useful to
    // know that the address is relative to the instruction address, but the comment is useful for understanding the disassembly.
    void commentIpRelative(SgAsmInstruction*);
};

} // namespace
} // namespace

#ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
BOOST_CLASS_EXPORT_KEY(Rose::BinaryAnalysis::DisassemblerX86);
#endif

#endif
#endif