3 #ifndef ROSE_DISASSEMBLER_X86_H
4 #define ROSE_DISASSEMBLER_X86_H
6 #include <featureTests.h>
7 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
8 #include "Disassembler.h"
10 #include "InstructionEnumsX86.h"
11 #include "Cxx_GrammarSerialization.h"
13 #include <boost/serialization/access.hpp>
14 #include <boost/serialization/base_object.hpp>
15 #include <boost/serialization/export.hpp>
16 #include <boost/serialization/split_member.hpp>
31 SgUnsignedCharList insnbuf;
37 bool branchPredictionEnabled;
38 bool rexPresent, rexW, rexR, rexX, rexB;
40 bool operandSizeOverride;
41 bool addressSizeOverride;
51 bool isUnconditionalJump;
54 : ip(0), insnbufat(0), segOverride(x86_segreg_none), branchPrediction(x86_branch_prediction_none),
55 branchPredictionEnabled(
false), rexPresent(
false), rexW(
false), rexR(
false), rexX(
false), rexB(
false),
56 sizeMustBe64Bit(
false), operandSizeOverride(
false), addressSizeOverride(
false), lock(
false),
57 repeatPrefix(
x86_repeat_none), modregrmByteSet(
false), modregrmByte(0), modeField(0), rmField(0),
58 modrm(NULL), reg(NULL), isUnconditionalJump(
false) {}
64 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
66 friend class boost::serialization::access;
69 void serialize_common(S &s,
const unsigned ) {
74 s & BOOST_SERIALIZATION_NVP(wordSize);
78 void save(S &s,
const unsigned version)
const {
79 serialize_common(s, version);
83 void load(S &s,
const unsigned version) {
84 serialize_common(s, version);
88 BOOST_SERIALIZATION_SPLIT_MEMBER();
98 : insnSize(x86_insnsize_none), wordSize(0) {}
102 : insnSize(x86_insnsize_none), wordSize(0) {
116 virtual Unparser::BasePtr
unparser() const ROSE_OVERRIDE;
119 AddressSet *successors=NULL) ROSE_OVERRIDE;
134 ExceptionX86(
const std::string &mesg,
const State &state)
135 : Exception(mesg, state.ip) {
136 ASSERT_require(state.insnbufat <= state.insnbuf.size());
137 if (state.insnbufat > 0)
138 bytes = SgUnsignedCharList(&state.insnbuf[0], &state.insnbuf[0] + state.insnbufat);
139 bit = 8 * state.insnbufat;
142 ExceptionX86(
const std::string &mesg,
const State &state,
size_t bit)
143 : Exception(mesg, state.ip) {
144 ASSERT_require(state.insnbufat <= state.insnbuf.size());
145 if (state.insnbufat > 0)
146 bytes = SgUnsignedCharList(&state.insnbuf[0], &state.insnbuf[0] + state.insnbufat);
153 rmLegacyByte, rmRexByte, rmWord, rmDWord, rmQWord, rmSegment, rmST, rmMM, rmXMM, rmControl, rmDebug, rmReturnNull
158 mmNone, mmF3, mm66, mmF2
170 uint8_t getByte(State &state)
const;
175 uint16_t getWord(State &state)
const;
180 uint32_t getDWord(State &state)
const;
185 uint64_t getQWord(State &state)
const;
201 RegisterMode effectiveOperandMode(State &state)
const {
202 return sizeToMode(effectiveOperandSize(state));
211 SgAsmType *effectiveOperandType(State &state)
const {
212 return sizeToType(effectiveOperandSize(state));
216 bool longMode()
const {
221 MMPrefix mmPrefix(State &state)
const;
224 void not64(State &state)
const {
226 throw ExceptionX86(
"not valid for 64-bit code", state);
231 void setRex(State &state, uint8_t prefix)
const;
249 SgAsmExpression *makeAddrSizeValue(State &state, int64_t val,
size_t bit_offset,
size_t bit_size)
const;
275 return makeRegister(state, fullRegisterNumber, effectiveOperandMode(state));
280 return makeRegister(state, registerNumber + (rexExtension ? 8 : 0), effectiveOperandMode(state));
306 void getModRegRM(State &state, RegisterMode regMode, RegisterMode rmMode,
SgAsmType *t,
SgAsmType *tForReg = NULL)
const;
313 void fillInModRM(State &state, RegisterMode rmMode,
SgAsmType *t)
const;
323 void requireMemory(State &state)
const {
324 if (!state.modregrmByteSet)
325 throw ExceptionX86(
"requires Mod/RM byte", state);
326 if (state.modeField == 3)
327 throw ExceptionX86(
"requires memory", state);
437 void init(
size_t wordsize);
439 #if 0 // is this ever used?
446 state.branchPredictionEnabled = state.branchPrediction != x86_branch_prediction_none;
452 void startInstruction(State &state, rose_addr_t start_va,
const uint8_t *buf,
size_t bufsz)
const {
454 state.insnbuf = SgUnsignedCharList(buf, buf+bufsz);
458 state.segOverride = x86_segreg_none;
459 state.branchPrediction = x86_branch_prediction_none;
460 state.branchPredictionEnabled =
false;
461 state.rexPresent = state.rexW = state.rexR = state.rexX = state.rexB =
false;
462 state.sizeMustBe64Bit =
false;
463 state.operandSizeOverride =
false;
464 state.addressSizeOverride =
false;
467 state.modregrmByteSet =
false;
468 state.modregrmByte = state.modeField = state.regField = state.rmField = 0;
469 state.modrm = state.reg = NULL;
470 state.isUnconditionalJump =
false;
481 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
Instruction is for a 64-bit architecture.
Base class for references to a machine register.
Base class for machine instructions.
X86BranchPrediction
Intel x86 branch prediction types.
Rose::BinaryAnalysis::X86InstructionSize get_baseSize() const
Property: An enum constant describing the base size of an x86 instruction.
Rose::BinaryAnalysis::X86BranchPrediction get_branchPrediction() const
Property: An enum constant describing branch prediction.
Rose::BinaryAnalysis::X86SegmentRegister get_segmentOverride() const
Property: The segment override register.
Main namespace for the ROSE library.
virtual Unparser::BasePtr unparser() const ROSE_OVERRIDE
Unparser.
virtual bool canDisassemble(SgAsmGenericHeader *) const ROSE_OVERRIDE
Predicate determining the suitability of a disassembler for a specific file header.
Reference to memory locations.
bool get_lockPrefix() const
Property: Whether the x86 lock prefix was present.
An efficient mapping from an address space to stored data.
virtual DisassemblerX86 * clone() const ROSE_OVERRIDE
Creates a new copy of a disassembler.
Represents one Intel x86 machine instruction.
Base class for expressions.
Base class for binary types.
virtual SgAsmInstruction * makeUnknownInstruction(const Exception &) ROSE_OVERRIDE
Makes an unknown instruction from an exception.
Disassembler for the x86 architecture.
X86SegmentRegister
Intel x86 segment registers.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &map, rose_addr_t start_va, AddressSet *successors=NULL) ROSE_OVERRIDE
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
X86InstructionKind
List of all x86 instructions known to the ROSE disassembler/assembler.
rose_addr_t get_address() const
Property: Starting virtual address.
Base class for all ROSE exceptions.
Virtual base class for instruction disassemblers.
X86InstructionSize
Intel x86 instruction size constants.
X86RepeatPrefix
Intel x86 instruction repeat prefix.