1#ifndef ROSE_BinaryAnalysis_InstructionSemantics_DispatcherCil_H
2#define ROSE_BinaryAnalysis_InstructionSemantics_DispatcherCil_H
3#include <featureTests.h>
4#ifdef ROSE_ENABLE_BINARY_ANALYSIS
6#include <Rose/BinaryAnalysis/BasicTypes.h>
7#include <Rose/BinaryAnalysis/InstructionSemantics/BaseSemantics.h>
8#include <Rose/BinaryAnalysis/InstructionEnumsCil.h>
10#include <boost/serialization/access.hpp>
11#include <boost/serialization/base_object.hpp>
12#include <boost/serialization/export.hpp>
13#include <boost/serialization/split_member.hpp>
16namespace BinaryAnalysis {
17namespace InstructionSemantics {
49#ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
51 friend class boost::serialization::access;
54 void save(S &s,
const unsigned )
const {
55 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(
Super);
59 void load(S &s,
const unsigned ) {
60 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(
Super);
66 BOOST_SERIALIZATION_SPLIT_MEMBER();
157#ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
Dispatches instructions through the RISC layer.
Base class for most instruction semantics RISC operators.
RegisterDescriptor REG_MACEXT2
Cached register.
static DispatcherCilPtr instance(const Architecture::BaseConstPtr &, const BaseSemantics::RiscOperatorsPtr &)
Constructor.
RegisterDescriptor REG_D[8]
Cached register.
RegisterDescriptor REG_EXC_INAN
Cached register.
RegisterDescriptor REG_MACSR_SU
Cached register.
void iproc_init()
Loads the iproc table with instruction processing functors.
void updateFpsrExcUnfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType, SgAsmType *rounding, SgAsmType *dstType)
Set or clear FPSR EXC UVFL bit.
void updateFpsrExcInan(const BaseSemantics::SValuePtr &a, SgAsmType *aType, const BaseSemantics::SValuePtr &b, SgAsmType *bType)
Set or clear FPSR EXC INAN bit.
virtual BaseSemantics::SValuePtr read(SgAsmExpression *, size_t value_nbits, size_t addr_nbits=0) override
Reads an R-value expression.
virtual int iprocKey(SgAsmInstruction *insn_) const override
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table.
RegisterDescriptor REG_EXC_IDE
Cached register.
RegisterDescriptor REG_EXC_OVFL
Cached register.
RegisterDescriptor REG_SR
Cached register.
RegisterDescriptor REG_FPCC_Z
Cached register.
RegisterDescriptor REG_FPCC_NAN
Cached register.
RegisterDescriptor REG_AEXC_INEX
Cached register.
void memory_init()
Make sure memory is set up correctly.
RegisterDescriptor REG_CCR
Cached register.
RegisterDescriptor REG_EXC_BSUN
Cached register.
RegisterDescriptor REG_AEXC_IOP
Cached register.
RegisterDescriptor REG_CCR_Z
Cached register.
RegisterDescriptor REG_CCR_N
Cached register.
void updateFpsrExcIde(const BaseSemantics::SValuePtr &a, SgAsmType *aType, const BaseSemantics::SValuePtr &b, SgAsmType *bType)
Set or clear FPSR EXC IDE bit.
RegisterDescriptor REG_MACEXT1
Cached register.
RegisterDescriptor REG_FP[8]
Cached register.
RegisterDescriptor REG_MACSR_Z
Cached register.
RegisterDescriptor REG_AEXC_UNFL
Cached register.
RegisterDescriptor REG_EXC_DZ
Cached register.
RegisterDescriptor REG_FPCC_I
Cached register.
BaseSemantics::SValuePtr condition(CilInstructionKind, BaseSemantics::RiscOperators *)
Determines if an instruction should branch.
RegisterDescriptor REG_MACSR_C
Cached register.
void updateFpsrExcInex()
Set or clear FPSR EXC INEX bit.
DispatcherCilPtr Ptr
Shared-ownership pointer.
RegisterDescriptor REG_AEXC_OVFL
Cached register.
RegisterDescriptor REG_SSP
Cached register.
RegisterDescriptor REG_CCR_C
Cached register.
RegisterDescriptor REG_CCR_X
Cached register.
RegisterDescriptor REG_PC
Cached register.
void updateFpsrExcOvfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType, SgAsmType *rounding, SgAsmType *dstType)
Set or clear FPSR EXC OVFL bit.
virtual RegisterDescriptor stackPointerRegister() const override
Returns the stack pointer register.
static DispatcherCilPtr instance(const Architecture::BaseConstPtr &)
Construct a prototypical dispatcher.
BaseSemantics::Dispatcher Super
Base type.
RegisterDescriptor REG_AEXC_DZ
Cached register.
RegisterDescriptor REG_MACSR_N
Cached register.
void regcache_init()
Load the cached register descriptors.
RegisterDescriptor REG_SR_S
Cached register.
RegisterDescriptor REG_EXC_OPERR
Cached register.
RegisterDescriptor REG_MACSR_FI
Cached register.
static DispatcherCilPtr promote(const BaseSemantics::DispatcherPtr &)
Dynamic cast to DispatcherCilPtr with assertion.
RegisterDescriptor REG_A[8]
Cached register.
RegisterDescriptor REG_MAC_MASK
Cached register.
virtual RegisterDescriptor instructionPointerRegister() const override
Returns the instruction pointer register.
RegisterDescriptor REG_EXC_INEX
Cached register.
RegisterDescriptor REG_VBR
Cached register.
RegisterDescriptor REG_FPCC_N
Cached register.
void accumulateFpExceptions()
Update accrued floating-point exceptions.
RegisterDescriptor REG_MACSR_V
Cached register.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &) const override
Virtual constructor.
RegisterDescriptor REG_CCR_V
Cached register.
RegisterDescriptor REG_MACEXT3
Cached register.
RegisterDescriptor REG_EXC_UNFL
Cached register.
RegisterDescriptor REG_MACEXT0
Cached register.
void adjustFpConditionCodes(const BaseSemantics::SValuePtr &result, SgAsmFloatType *)
Set floating point condition codes according to result.
Describes (part of) a physical CPU register.
Base class for expressions.
Base class for machine instructions.
Base class for binary types.
std::shared_ptr< const Base > BaseConstPtr
Reference counted pointer for Architecture::Base.
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
boost::shared_ptr< class DispatcherCil > DispatcherCilPtr
Shared-ownership pointer to an CIL instruction dispatcher.