ROSE  0.11.83.1
DispatcherCil.h
1 #ifndef ROSE_BinaryAnalysis_InstructionSemantics2_DispatcherCil_H
2 #define ROSE_BinaryAnalysis_InstructionSemantics2_DispatcherCil_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
5 
6 #include <Rose/BinaryAnalysis/InstructionSemantics2/BaseSemantics.h>
7 
8 #include <boost/serialization/access.hpp>
9 #include <boost/serialization/base_object.hpp>
10 #include <boost/serialization/export.hpp>
11 #include <boost/serialization/split_member.hpp>
12 
13 namespace Rose {
14 namespace BinaryAnalysis {
15 namespace InstructionSemantics2 {
16 
18 typedef boost::shared_ptr<class DispatcherCil> DispatcherCilPtr;
19 
21 public:
24 
27 
28 public:
38  // Floating-point condition code bits
40  // Floating-point status register exception bits
43  // Floating-point status register accrued exception bits
47 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
48 private:
49  friend class boost::serialization::access;
50 
51  template<class S>
52  void save(S &s, const unsigned /*version*/) const {
53  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
54  };
55 
56  template<class S>
57  void load(S &s, const unsigned /*version*/) {
58  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
59  regcache_init();
60  iproc_init();
61  memory_init();
62  }
63 
64  BOOST_SERIALIZATION_SPLIT_MEMBER();
65 #endif
66 
67 protected:
68  // prototypical constructor
69  DispatcherCil(): BaseSemantics::Dispatcher(32, RegisterDictionary::dictionary_coldfire_emac()) {}
70 
71  DispatcherCil(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
72  : BaseSemantics::Dispatcher(ops, addrWidth, regs ? regs : RegisterDictionary::dictionary_coldfire_emac()) {
73  ASSERT_require(32==addrWidth);
74  regcache_init();
75  iproc_init();
76  memory_init();
77  initializeState(ops->currentState());
78  }
79 
81  void iproc_init();
82 
86  void regcache_init();
87 
89  void memory_init();
90 
91 public:
94  static DispatcherCilPtr instance() {
95  return DispatcherCilPtr(new DispatcherCil);
96  }
97 
99  static DispatcherCilPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth,
100  const RegisterDictionary *regs=NULL) {
101  return DispatcherCilPtr(new DispatcherCil(ops, addrWidth, regs));
102  }
103 
106  const RegisterDictionary *regs=NULL) const override {
107  if (0==addrWidth)
108  addrWidth = addressWidth();
109  if (!regs)
110  regs = registerDictionary();
111  return instance(ops, addrWidth, regs);
112  }
113 
115  static DispatcherCilPtr promote(const BaseSemantics::DispatcherPtr &d) {
116  DispatcherCilPtr retval = boost::dynamic_pointer_cast<DispatcherCil>(d);
117  ASSERT_not_null(retval);
118  return retval;
119  }
120 
121  virtual void set_register_dictionary(const RegisterDictionary *regdict) override;
122 
123  virtual RegisterDescriptor instructionPointerRegister() const override;
124  virtual RegisterDescriptor stackPointerRegister() const override;
125  virtual RegisterDescriptor stackFrameRegister() const override;
126  virtual RegisterDescriptor callReturnRegister() const override;
127 
128  virtual int iprocKey(SgAsmInstruction *insn_) const override {
129  SgAsmCilInstruction *insn = isSgAsmCilInstruction(insn_);
130  ASSERT_not_null(insn);
131  return insn->get_kind();
132  }
133 
134  virtual BaseSemantics::SValuePtr read(SgAsmExpression*, size_t value_nbits, size_t addr_nbits=0) override;
135 
138  const BaseSemantics::SValuePtr &b, SgAsmType *bType);
139 
142  const BaseSemantics::SValuePtr &b, SgAsmType *bType);
143 
149  void updateFpsrExcOvfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType,
150  SgAsmType *rounding, SgAsmType *dstType);
151 
159  void updateFpsrExcUnfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType,
160  SgAsmType *rounding, SgAsmType *dstType);
161 
163  void updateFpsrExcInex();
164 
167 
169  void accumulateFpExceptions();
170 
173 };
174 
175 } // namespace
176 } // namespace
177 } // namespace
178 
179 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
181 #endif
182 
183 #endif
184 #endif
const RegisterDictionary * registerDictionary() const
Property: Register dictionary.
Definition: Dispatcher.h:195
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
virtual void initializeState(const StatePtr &)
Initialize the state.
RegisterDescriptor REG_EXC_OPERR
Cached register.
Definition: DispatcherCil.h:41
void updateFpsrExcOvfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType, SgAsmType *rounding, SgAsmType *dstType)
Set or clear FPSR EXC OVFL bit.
RegisterDescriptor REG_D[8]
Cached register.
Definition: DispatcherCil.h:35
Base class for machine instructions.
void updateFpsrExcIde(const BaseSemantics::SValuePtr &a, SgAsmType *aType, const BaseSemantics::SValuePtr &b, SgAsmType *bType)
Set or clear FPSR EXC IDE bit.
RegisterDescriptor REG_EXC_INEX
Cached register.
Definition: DispatcherCil.h:42
static DispatcherCilPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
Definition: DispatcherCil.h:99
void updateFpsrExcInex()
Set or clear FPSR EXC INEX bit.
RegisterDescriptor REG_EXC_OVFL
Cached register.
Definition: DispatcherCil.h:41
DispatcherCilPtr Ptr
Shared-ownership pointer.
Definition: DispatcherCil.h:26
CilInstructionKind
CIL instruction types.
void updateFpsrExcUnfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType, SgAsmType *rounding, SgAsmType *dstType)
Set or clear FPSR EXC UVFL bit.
RegisterDescriptor REG_AEXC_INEX
Cached register.
Definition: DispatcherCil.h:44
Main namespace for the ROSE library.
RegisterDescriptor REG_MAC_MASK
Cached register.
Definition: DispatcherCil.h:36
RegisterDescriptor REG_EXC_UNFL
Cached register.
Definition: DispatcherCil.h:41
virtual RegisterDescriptor stackFrameRegister() const override
Returns the stack call frame register.
BaseSemantics::SValuePtr condition(CilInstructionKind, BaseSemantics::RiscOperators *)
Determines if an instruction should branch.
void accumulateFpExceptions()
Update accrued floating-point exceptions.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
Rose::BinaryAnalysis::CilInstructionKind get_kind() const
Property: Instruction kind.
RegisterDescriptor REG_FP[8]
Cached register.
Definition: DispatcherCil.h:35
Base classes for instruction semantics.
Definition: Dispatcher.h:18
virtual BaseSemantics::SValuePtr read(SgAsmExpression *, size_t value_nbits, size_t addr_nbits=0) override
Reads an R-value expression.
void memory_init()
Make sure memory is set up correctly.
Describes (part of) a physical CPU register.
size_t addressWidth() const
Property: Width of memory addresses.
Definition: Dispatcher.h:225
void adjustFpConditionCodes(const BaseSemantics::SValuePtr &result, SgAsmFloatType *)
Set floating point condition codes according to result.
static DispatcherCilPtr promote(const BaseSemantics::DispatcherPtr &d)
Dynamic cast to DispatcherCilPtr with assertion.
boost::shared_ptr< class DispatcherCil > DispatcherCilPtr
Shared-ownership pointer to an CIL instruction dispatcher.
Definition: DispatcherCil.h:18
RegisterDescriptor REG_AEXC_UNFL
Cached register.
Definition: DispatcherCil.h:44
void updateFpsrExcInan(const BaseSemantics::SValuePtr &a, SgAsmType *aType, const BaseSemantics::SValuePtr &b, SgAsmType *bType)
Set or clear FPSR EXC INAN bit.
virtual RegisterDescriptor instructionPointerRegister() const override
Returns the instruction pointer register.
RegisterDescriptor REG_AEXC_IOP
Cached register.
Definition: DispatcherCil.h:44
Base class for most instruction semantics RISC operators.
Definition: RiscOperators.h:48
const RegisterDictionary * regdict
See registerDictionary property.
Definition: Dispatcher.h:53
Base class for expressions.
Dispatches instructions through the RISC layer.
Definition: Dispatcher.h:44
RegisterDescriptor REG_MACSR_SU
Cached register.
Definition: DispatcherCil.h:36
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0, const RegisterDictionary *regs=NULL) const override
Virtual constructor.
Base class for binary types.
RegisterDescriptor REG_EXC_INAN
Cached register.
Definition: DispatcherCil.h:41
RegisterDescriptor REG_AEXC_OVFL
Cached register.
Definition: DispatcherCil.h:44
static DispatcherCilPtr instance()
Construct a prototypical dispatcher.
Definition: DispatcherCil.h:94
Defines registers available for a particular architecture.
Definition: Registers.h:37
RegisterDescriptor REG_MACSR_FI
Cached register.
Definition: DispatcherCil.h:36
virtual RegisterDescriptor stackPointerRegister() const override
Returns the stack pointer register.
RegisterDescriptor REG_EXC_BSUN
Cached register.
Definition: DispatcherCil.h:41
RegisterDescriptor REG_A[8]
Cached register.
Definition: DispatcherCil.h:35
Floating point types.
void iproc_init()
Loads the iproc table with instruction processing functors.
void regcache_init()
Load the cached register descriptors.
virtual int iprocKey(SgAsmInstruction *insn_) const override
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
virtual RegisterDescriptor callReturnRegister() const override
Returns the function call return address register.
RegisterDescriptor REG_FPCC_NAN
Cached register.
Definition: DispatcherCil.h:39