ROSE  0.11.98.0
DispatcherCil.h
1 #ifndef ROSE_BinaryAnalysis_InstructionSemantics_DispatcherCil_H
2 #define ROSE_BinaryAnalysis_InstructionSemantics_DispatcherCil_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
5 
6 #include <Rose/BinaryAnalysis/BasicTypes.h>
7 #include <Rose/BinaryAnalysis/RegisterDictionary.h>
8 #include <Rose/BinaryAnalysis/InstructionSemantics/BaseSemantics.h>
9 
10 #include <boost/serialization/access.hpp>
11 #include <boost/serialization/base_object.hpp>
12 #include <boost/serialization/export.hpp>
13 #include <boost/serialization/split_member.hpp>
14 
15 namespace Rose {
16 namespace BinaryAnalysis {
17 namespace InstructionSemantics {
18 
20 typedef boost::shared_ptr<class DispatcherCil> DispatcherCilPtr;
21 
23 public:
26 
29 
30 public:
40  // Floating-point condition code bits
42  // Floating-point status register exception bits
45  // Floating-point status register accrued exception bits
49 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
50 private:
51  friend class boost::serialization::access;
52 
53  template<class S>
54  void save(S &s, const unsigned /*version*/) const {
55  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
56  };
57 
58  template<class S>
59  void load(S &s, const unsigned /*version*/) {
60  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
61  regcache_init();
62  iproc_init();
63  memory_init();
64  }
65 
66  BOOST_SERIALIZATION_SPLIT_MEMBER();
67 #endif
68 
69 protected:
70  // prototypical constructor
71  DispatcherCil();
72 
73  DispatcherCil(const BaseSemantics::RiscOperatorsPtr&, size_t addrWidth, const RegisterDictionaryPtr&);
74 
76  void iproc_init();
77 
81  void regcache_init();
82 
84  void memory_init();
85 
86 public:
87  ~DispatcherCil();
88 
91  static DispatcherCilPtr instance();
92 
94  static DispatcherCilPtr instance(const BaseSemantics::RiscOperatorsPtr&, size_t addrWidth, const RegisterDictionaryPtr&);
95 
98  const RegisterDictionaryPtr&) const override;
99 
101  static DispatcherCilPtr promote(const BaseSemantics::DispatcherPtr&);
102 
103  virtual void set_register_dictionary(const RegisterDictionaryPtr&) override;
104 
105  virtual RegisterDescriptor instructionPointerRegister() const override;
106  virtual RegisterDescriptor stackPointerRegister() const override;
107  virtual RegisterDescriptor stackFrameRegister() const override;
108  virtual RegisterDescriptor callReturnRegister() const override;
109 
110  virtual int iprocKey(SgAsmInstruction *insn_) const override {
111  SgAsmCilInstruction *insn = isSgAsmCilInstruction(insn_);
112  ASSERT_not_null(insn);
113  return insn->get_kind();
114  }
115 
116  virtual BaseSemantics::SValuePtr read(SgAsmExpression*, size_t value_nbits, size_t addr_nbits=0) override;
117 
120  const BaseSemantics::SValuePtr &b, SgAsmType *bType);
121 
124  const BaseSemantics::SValuePtr &b, SgAsmType *bType);
125 
131  void updateFpsrExcOvfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType,
132  SgAsmType *rounding, SgAsmType *dstType);
133 
141  void updateFpsrExcUnfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType,
142  SgAsmType *rounding, SgAsmType *dstType);
143 
145  void updateFpsrExcInex();
146 
149 
151  void accumulateFpExceptions();
152 
155 };
156 
157 } // namespace
158 } // namespace
159 } // namespace
160 
161 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
163 #endif
164 
165 #endif
166 #endif
void memory_init()
Make sure memory is set up correctly.
RegisterDescriptor REG_EXC_INEX
Cached register.
Definition: DispatcherCil.h:44
RegisterDescriptor REG_AEXC_DZ
Cached register.
Definition: DispatcherCil.h:46
RegisterDescriptor REG_AEXC_INEX
Cached register.
Definition: DispatcherCil.h:46
RegisterDescriptor REG_FPCC_N
Cached register.
Definition: DispatcherCil.h:41
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
RegisterDescriptor REG_EXC_OPERR
Cached register.
Definition: DispatcherCil.h:43
void updateFpsrExcInex()
Set or clear FPSR EXC INEX bit.
Base class for machine instructions.
virtual int iprocKey(SgAsmInstruction *insn_) const override
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
RegisterDescriptor REG_MACSR_FI
Cached register.
Definition: DispatcherCil.h:38
RegisterDescriptor REG_AEXC_UNFL
Cached register.
Definition: DispatcherCil.h:46
RegisterDescriptor REG_FPCC_Z
Cached register.
Definition: DispatcherCil.h:41
virtual RegisterDescriptor stackFrameRegister() const override
Returns the stack call frame register.
RegisterDescriptor REG_FP[8]
Cached register.
Definition: DispatcherCil.h:37
RegisterDescriptor REG_FPCC_I
Cached register.
Definition: DispatcherCil.h:41
RegisterDescriptor REG_EXC_OVFL
Cached register.
Definition: DispatcherCil.h:43
void regcache_init()
Load the cached register descriptors.
virtual RegisterDescriptor callReturnRegister() const override
Returns the function call return address register.
RegisterDescriptor REG_EXC_BSUN
Cached register.
Definition: DispatcherCil.h:43
Main namespace for the ROSE library.
RegisterDescriptor REG_AEXC_OVFL
Cached register.
Definition: DispatcherCil.h:46
virtual RegisterDescriptor instructionPointerRegister() const override
Returns the instruction pointer register.
RegisterDescriptor REG_MAC_MASK
Cached register.
Definition: DispatcherCil.h:38
RegisterDescriptor REG_MACSR_C
Cached register.
Definition: DispatcherCil.h:38
RegisterDescriptor REG_D[8]
Cached register.
Definition: DispatcherCil.h:37
RegisterDescriptor REG_MACEXT2
Cached register.
Definition: DispatcherCil.h:39
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
Dispatches instructions through the RISC layer.
Definition: Dispatcher.h:44
Rose::BinaryAnalysis::CilInstructionKind get_kind() const
Property: Instruction kind.
RegisterDescriptor REG_FPCC_NAN
Cached register.
Definition: DispatcherCil.h:41
RegisterDescriptor REG_MACEXT0
Cached register.
Definition: DispatcherCil.h:39
RegisterDescriptor REG_MACEXT3
Cached register.
Definition: DispatcherCil.h:39
BaseSemantics::SValuePtr condition(CilInstructionKind, BaseSemantics::RiscOperators *)
Determines if an instruction should branch.
Describes (part of) a physical CPU register.
boost::shared_ptr< class DispatcherCil > DispatcherCilPtr
Shared-ownership pointer to an CIL instruction dispatcher.
Definition: DispatcherCil.h:20
RegisterDescriptor REG_MACSR_V
Cached register.
Definition: DispatcherCil.h:38
void updateFpsrExcUnfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType, SgAsmType *rounding, SgAsmType *dstType)
Set or clear FPSR EXC UVFL bit.
void adjustFpConditionCodes(const BaseSemantics::SValuePtr &result, SgAsmFloatType *)
Set floating point condition codes according to result.
RegisterDescriptor REG_EXC_IDE
Cached register.
Definition: DispatcherCil.h:44
RegisterDescriptor REG_EXC_UNFL
Cached register.
Definition: DispatcherCil.h:43
RegisterDescriptor REG_AEXC_IOP
Cached register.
Definition: DispatcherCil.h:46
Base class for expressions.
Binary analysis.
RegisterDescriptor REG_MACSR_Z
Cached register.
Definition: DispatcherCil.h:38
void updateFpsrExcInan(const BaseSemantics::SValuePtr &a, SgAsmType *aType, const BaseSemantics::SValuePtr &b, SgAsmType *bType)
Set or clear FPSR EXC INAN bit.
RegisterDescriptor REG_EXC_INAN
Cached register.
Definition: DispatcherCil.h:43
static DispatcherCilPtr promote(const BaseSemantics::DispatcherPtr &)
Dynamic cast to DispatcherCilPtr with assertion.
Base class for binary types.
void iproc_init()
Loads the iproc table with instruction processing functors.
RegisterDescriptor REG_MACSR_N
Cached register.
Definition: DispatcherCil.h:38
RegisterDescriptor REG_A[8]
Cached register.
Definition: DispatcherCil.h:37
DispatcherCilPtr Ptr
Shared-ownership pointer.
Definition: DispatcherCil.h:28
static DispatcherCilPtr instance()
Construct a prototypical dispatcher.
Base class for most instruction semantics RISC operators.
Definition: RiscOperators.h:48
virtual BaseSemantics::SValuePtr read(SgAsmExpression *, size_t value_nbits, size_t addr_nbits=0) override
Reads an R-value expression.
RegisterDescriptor REG_EXC_DZ
Cached register.
Definition: DispatcherCil.h:43
void updateFpsrExcIde(const BaseSemantics::SValuePtr &a, SgAsmType *aType, const BaseSemantics::SValuePtr &b, SgAsmType *bType)
Set or clear FPSR EXC IDE bit.
RegisterDescriptor REG_MACSR_SU
Cached register.
Definition: DispatcherCil.h:38
void updateFpsrExcOvfl(const BaseSemantics::SValuePtr &intermediate, SgAsmType *valueType, SgAsmType *rounding, SgAsmType *dstType)
Set or clear FPSR EXC OVFL bit.
Floating point types.
RegisterDescriptor REG_MACEXT1
Cached register.
Definition: DispatcherCil.h:39
virtual RegisterDescriptor stackPointerRegister() const override
Returns the stack pointer register.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &, size_t addrWidth, const RegisterDictionaryPtr &) const override
Virtual constructor.
void accumulateFpExceptions()
Update accrued floating-point exceptions.