Description

Definition at line 22 of file DispatcherCil.h.

Inheritance diagram for Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil:

Collaboration diagram for Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil:

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Public Types
using	Super = BaseSemantics::Dispatcher
	Base type.

using	Ptr = DispatcherCilPtr
	Shared-ownership pointer.

Public Types inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher
using	Ptr = DispatcherPtr
	Shared-ownership pointer.

Public Member Functions
virtual BaseSemantics::DispatcherPtr	create (const BaseSemantics::RiscOperatorsPtr &) const override
	Virtual constructor.

virtual RegisterDescriptor	instructionPointerRegister () const override
	Returns the instruction pointer register.

virtual RegisterDescriptor	stackPointerRegister () const override
	Returns the stack pointer register.

virtual int	iprocKey (SgAsmInstruction *insn_) const override
	Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table.

virtual BaseSemantics::SValuePtr	read (SgAsmExpression *, size_t value_nbits, size_t addr_nbits=0) override
	Reads an R-value expression.

void	updateFpsrExcInan (const BaseSemantics::SValuePtr &a, SgAsmType aType, const BaseSemantics::SValuePtr &b, SgAsmType bType)
	Set or clear FPSR EXC INAN bit.

void	updateFpsrExcIde (const BaseSemantics::SValuePtr &a, SgAsmType aType, const BaseSemantics::SValuePtr &b, SgAsmType bType)
	Set or clear FPSR EXC IDE bit.

void	updateFpsrExcOvfl (const BaseSemantics::SValuePtr &intermediate, SgAsmType valueType, SgAsmType rounding, SgAsmType *dstType)
	Set or clear FPSR EXC OVFL bit.

void	updateFpsrExcUnfl (const BaseSemantics::SValuePtr &intermediate, SgAsmType valueType, SgAsmType rounding, SgAsmType *dstType)
	Set or clear FPSR EXC UVFL bit.

void	updateFpsrExcInex ()
	Set or clear FPSR EXC INEX bit.

BaseSemantics::SValuePtr	condition (CilInstructionKind, BaseSemantics::RiscOperators *)
	Determines if an instruction should branch.

void	accumulateFpExceptions ()
	Update accrued floating-point exceptions.

void	adjustFpConditionCodes (const BaseSemantics::SValuePtr &result, SgAsmFloatType *)
	Set floating point condition codes according to result.

Public Member Functions inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher
virtual void	processInstruction (SgAsmInstruction *insn)
	Process a single instruction.

virtual void	processDelaySlot (SgAsmInstruction *delayInsn)
	Process a delay slot.

virtual InsnProcessor *	iprocLookup (SgAsmInstruction *insn)
	Lookup the processor for an instruction.

virtual void	iprocReplace (SgAsmInstruction insn, InsnProcessor iproc)
	Replace an instruction processor with another.

virtual void	iprocSet (int key, InsnProcessor *iproc)
	Set an iproc table entry to the specified value.

virtual InsnProcessor *	iprocGet (int key)
	Obtain an iproc table entry for the specified key.

Architecture::BaseConstPtr	architecture () const
	Property: Architecture.

virtual StatePtr	currentState () const
	Get a pointer to the state object.

virtual SValuePtr	protoval () const
	Return the prototypical value.

virtual SgAsmInstruction *	currentInstruction () const
	Returns the instruction that is being processed.

virtual SValuePtr	number_ (size_t nbits, uint64_t number) const
	Return a semantic value representing a number.

RegisterDictionaryPtr	registerDictionary () const
	Property: Register dictionary.

virtual RegisterDescriptor	findRegister (const std::string &regname, size_t nbits=0, bool allowMissing=false) const
	Lookup a register by name.

size_t	addressWidth () const
	Property: Width of memory addresses in bits.

virtual RegisterDescriptor	stackFrameRegister () const
	Returns the stack call frame register.

virtual RegisterDescriptor	callReturnRegister () const
	Returns the function call return address register.

virtual void	initializeState (const StatePtr &)
	Initialize the state.

virtual void	advanceInstructionPointer (SgAsmInstruction *)
	Update the instruction pointer register.

virtual RegisterDescriptor	segmentRegister (SgAsmMemoryReferenceExpression *)
	Returns a register descriptor for the segment part of a memory reference expression.

virtual void	incrementRegisters (SgAsmExpression *)
	Increment all auto-increment registers in the expression.

virtual void	decrementRegisters (SgAsmExpression *)
	Decrement all auto-decrement registers in the expression.

virtual void	preUpdate (SgAsmExpression *, const BaseSemantics::SValuePtr &enabled)
	Update registers for pre-add expressions.

virtual void	postUpdate (SgAsmExpression *, const BaseSemantics::SValuePtr &enabled)
	Update registers for post-add expressions.

virtual SValuePtr	effectiveAddress (SgAsmExpression *, size_t nbits=0)
	Returns a memory address by evaluating the address expression.

virtual void	write (SgAsmExpression *, const SValuePtr &value, size_t addr_nbits=0)
	Writes to an L-value expression.

virtual RiscOperatorsPtr	operators () const
	Property: RISC operators.

virtual void	operators (const RiscOperatorsPtr &)
	Property: RISC operators.

virtual SValuePtr	undefined_ (size_t nbits) const
	Return a new undefined semantic value.

virtual SValuePtr	unspecified_ (size_t nbits) const
	Return a new undefined semantic value.

bool	autoResetInstructionPointer () const
	Property: Reset instruction pointer register for each instruction.

void	autoResetInstructionPointer (bool b)
	Property: Reset instruction pointer register for each instruction.

Static Public Member Functions
static DispatcherCilPtr	instance (const Architecture::BaseConstPtr &)
	Construct a prototypical dispatcher.

static DispatcherCilPtr	instance (const Architecture::BaseConstPtr &, const BaseSemantics::RiscOperatorsPtr &)
	Constructor.

static DispatcherCilPtr	promote (const BaseSemantics::DispatcherPtr &)
	Dynamic cast to DispatcherCilPtr with assertion.

Public Attributes

RegisterDescriptor	REG_D [8]
	Cached register.

RegisterDescriptor	REG_A [8]
	Cached register.

RegisterDescriptor	REG_FP [8]
	Cached register.

RegisterDescriptor	REG_PC
	Cached register.

RegisterDescriptor	REG_CCR
	Cached register.

RegisterDescriptor	REG_CCR_C
	Cached register.

RegisterDescriptor	REG_CCR_V
	Cached register.

RegisterDescriptor	REG_CCR_Z
	Cached register.

RegisterDescriptor	REG_CCR_N
	Cached register.

RegisterDescriptor	REG_CCR_X
	Cached register.

RegisterDescriptor	REG_MACSR_SU
	Cached register.

RegisterDescriptor	REG_MACSR_FI
	Cached register.

RegisterDescriptor	REG_MACSR_N
	Cached register.

RegisterDescriptor	REG_MACSR_Z
	Cached register.

RegisterDescriptor	REG_MACSR_V
	Cached register.

RegisterDescriptor	REG_MACSR_C
	Cached register.

RegisterDescriptor	REG_MAC_MASK
	Cached register.

RegisterDescriptor	REG_MACEXT0
	Cached register.

RegisterDescriptor	REG_MACEXT1
	Cached register.

RegisterDescriptor	REG_MACEXT2
	Cached register.

RegisterDescriptor	REG_MACEXT3
	Cached register.

RegisterDescriptor	REG_SSP
	Cached register.

RegisterDescriptor	REG_SR_S
	Cached register.

RegisterDescriptor	REG_SR
	Cached register.

RegisterDescriptor	REG_VBR
	Cached register.

RegisterDescriptor	REG_FPCC_NAN
	Cached register.

RegisterDescriptor	REG_FPCC_I
	Cached register.

RegisterDescriptor	REG_FPCC_Z
	Cached register.

RegisterDescriptor	REG_FPCC_N
	Cached register.

RegisterDescriptor	REG_EXC_BSUN
	Cached register.

RegisterDescriptor	REG_EXC_OPERR
	Cached register.

RegisterDescriptor	REG_EXC_OVFL
	Cached register.

RegisterDescriptor	REG_EXC_UNFL
	Cached register.

RegisterDescriptor	REG_EXC_DZ
	Cached register.

RegisterDescriptor	REG_EXC_INAN
	Cached register.

RegisterDescriptor	REG_EXC_IDE
	Cached register.

RegisterDescriptor	REG_EXC_INEX
	Cached register.

RegisterDescriptor	REG_AEXC_IOP
	Cached register.

RegisterDescriptor	REG_AEXC_OVFL
	Cached register.

RegisterDescriptor	REG_AEXC_UNFL
	Cached register.

RegisterDescriptor	REG_AEXC_DZ
	Cached register.

RegisterDescriptor	REG_AEXC_INEX
	Cached register.

Protected Member Functions
	DispatcherCil (const Architecture::BaseConstPtr &)

	DispatcherCil (const Architecture::BaseConstPtr &, const BaseSemantics::RiscOperatorsPtr &)

void	iproc_init ()
	Loads the iproc table with instruction processing functors.

void	regcache_init ()
	Load the cached register descriptors.

void	memory_init ()
	Make sure memory is set up correctly.

Protected Member Functions inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher
	Dispatcher (const Architecture::BaseConstPtr &)

	Dispatcher (const Architecture::BaseConstPtr &, const RiscOperatorsPtr &)

virtual void	processCommon ()

Additional Inherited Members
Protected Types inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher
typedef std::vector< InsnProcessor * >	InsnProcessors

Protected Attributes inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher
bool	autoResetInstructionPointer_ = true
	Reset instruction pointer register for each instruction.

InsnProcessors	iproc_table

Member Typedef Documentation

◆ Super

using Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::Super = BaseSemantics::Dispatcher

Base type.

Definition at line 25 of file DispatcherCil.h.

◆ Ptr

using Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::Ptr = DispatcherCilPtr

Shared-ownership pointer.

Definition at line 28 of file DispatcherCil.h.

Member Function Documentation

◆ iproc_init()

void Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::iproc_init ( )

protected

Loads the iproc table with instruction processing functors.

This normally happens from the constructor.

◆ regcache_init()

void Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::regcache_init ( )

protected

Load the cached register descriptors.

This happens at construction when the registerDictionary property is changed.

◆ memory_init()

void Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::memory_init ( )

protected

Make sure memory is set up correctly.

For instance, byte order should be big endian.

◆ instance()

static DispatcherCilPtr Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::instance ( const Architecture::BaseConstPtr & )

static

Construct a prototypical dispatcher.

The only thing this dispatcher can be used for is to create another dispatcher with the virtual create method.

◆ create()

virtual BaseSemantics::DispatcherPtr Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::create ( const BaseSemantics::RiscOperatorsPtr & ) const

overridevirtual

Virtual constructor.

Implements Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.

◆ instructionPointerRegister()

virtual RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::instructionPointerRegister ( ) const

overridevirtual

Returns the instruction pointer register.

Reimplemented from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.

◆ stackPointerRegister()

virtual RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::stackPointerRegister ( ) const

overridevirtual

Returns the stack pointer register.

Reimplemented from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.

◆ iprocKey()

virtual int Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::iprocKey ( SgAsmInstruction * ) const

overridevirtual

Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table.

Implements Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.

◆ read()

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::read	(	SgAsmExpression *	,
		size_t	value_nbits,
		size_t	addr_nbits = `0`
	)

overridevirtual

Reads an R-value expression.

The expression can be a constant, register reference, or memory reference. The width of the returned value is specified by the value_nbits argument, and if this argument is zero then the width of the expression type is used. The width of the address passed to lower-level memory access functions is specified by addr_nbits. If addr_nbits is zero then the natural width of the effective address is passed to lower level functions.

Reimplemented from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.

◆ updateFpsrExcOvfl()

void Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::updateFpsrExcOvfl	(	const BaseSemantics::SValuePtr &	intermediate,
		SgAsmType *	valueType,
		SgAsmType *	rounding,
		SgAsmType *	dstType
	)

Set or clear FPSR EXC OVFL bit.

Set if the destination is a floating-point data register or memory (dstType) and the intermediate result (intermediate) has an exponent that is greater than or equal to the maximum exponent value of the selected rounding precision (rounding)

◆ updateFpsrExcUnfl()

void Rose::BinaryAnalysis::InstructionSemantics::DispatcherCil::updateFpsrExcUnfl	(	const BaseSemantics::SValuePtr &	intermediate,
		SgAsmType *	valueType,
		SgAsmType *	rounding,
		SgAsmType *	dstType
	)

Set or clear FPSR EXC UVFL bit.

Set if the intermediate result of an arithmetic instruction is too small to be represented as a normalized number in a floating-point register or memory using the selected rounding precision, that is, when the intermediate result exponent is less than or equal to the minimum exponent value of the selected rounding precision. Cleared otherwise. Underflow can ony occur when the desitnation format is single or double precision. When the destination is byte, word, or longword, the conversion ounderflows to zero without causing an underflow or an operand error.