ROSE  0.9.11.158
DispatcherPowerpc.h
1 // Semantics for 32-bit Motorola-IBM PowerPC microprocessors using ROSE instruction semantics API2
2 // This code was derived from $ROSE/projects/assemblyToSourceAst/powerpcInstructionSemantics.h,
3 // which is mostly a copy of $ROSE/projects/SemanticSignatureVectors/powerpcInstructionSemantics.h
4 //
5 // The ROSE style guide indicates that PowerPC, when used as part of a symbol in ROSE source code,
6 // should be capitalized as "Powerpc" (e.g., "DispatcherPowerpc", the same rule that consistently
7 // capitializes x86 as "DispatcherX86").
8 
9 #ifndef ROSE_DispatcherPpc_H
10 #define ROSE_DispatcherPpc_H
11 
12 #include "BaseSemantics2.h"
13 
14 #include <boost/serialization/access.hpp>
15 #include <boost/serialization/base_object.hpp>
16 #include <boost/serialization/export.hpp>
17 #include <boost/serialization/split_member.hpp>
18 
19 namespace Rose {
20 namespace BinaryAnalysis {
21 namespace InstructionSemantics2 {
22 
24 typedef boost::shared_ptr<class DispatcherPowerpc> DispatcherPowerpcPtr;
25 
27 public:
29 
37 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
38 private:
39  friend class boost::serialization::access;
40 
41  template<class S>
42  void save(S &s, const unsigned /*version*/) const {
43  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
44  }
45 
46  template<class S>
47  void load(S &s, const unsigned /*version*/) {
48  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
49  regcache_init();
50  iproc_init();
51  memory_init();
52  }
53 
54  BOOST_SERIALIZATION_SPLIT_MEMBER();
55 #endif
56 
57 protected:
58  // Prototypical constructor
59  DispatcherPowerpc(): BaseSemantics::Dispatcher(32, RegisterDictionary::dictionary_powerpc32()) {}
60 
61  // Prototypical constructor
62  DispatcherPowerpc(size_t addrWidth, const RegisterDictionary *regs/*=NULL*/)
63  : BaseSemantics::Dispatcher(addrWidth, regs ? regs : SgAsmPowerpcInstruction::registersForWidth(addrWidth)) {}
64 
65  DispatcherPowerpc(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
66  : BaseSemantics::Dispatcher(ops, addrWidth, regs ? regs : SgAsmPowerpcInstruction::registersForWidth(addrWidth)) {
67  ASSERT_require(32==addrWidth || 64==addrWidth);
68  regcache_init();
69  iproc_init();
70  memory_init();
71  }
72 
74  void iproc_init();
75 
77  void regcache_init();
78 
80  void memory_init();
81 
82 public:
85  static DispatcherPowerpcPtr instance() {
87  }
88 
90  static DispatcherPowerpcPtr instance(size_t addrWidth, const RegisterDictionary *regs = NULL) {
91  return DispatcherPowerpcPtr(new DispatcherPowerpc(addrWidth, regs));
92  }
93 
95  static DispatcherPowerpcPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth,
96  const RegisterDictionary *regs=NULL) {
97  return DispatcherPowerpcPtr(new DispatcherPowerpc(ops, addrWidth, regs));
98  }
99 
102  const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE {
103  if (0==addrWidth)
104  addrWidth = addressWidth();
105  if (!regs)
106  regs = get_register_dictionary();
107  return instance(ops, addrWidth, regs);
108  }
109 
111  static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &d) {
112  DispatcherPowerpcPtr retval = boost::dynamic_pointer_cast<DispatcherPowerpc>(d);
113  assert(retval!=NULL);
114  return retval;
115  }
116 
117  virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE;
118 
119  virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE;
120  virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE;
121  virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE;
122 
123  virtual int iproc_key(SgAsmInstruction *insn_) const ROSE_OVERRIDE {
124  SgAsmPowerpcInstruction *insn = isSgAsmPowerpcInstruction(insn_);
125  assert(insn!=NULL);
126  return insn->get_kind();
127  }
128 
133  void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow);
134 
136  virtual void updateCr0(const BaseSemantics::SValuePtr &result);
137 
141 
146 };
147 
148 } // namespace
149 } // namespace
150 } // namespace
151 
152 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
154 #endif
155 
156 #endif
virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE
Returns the stack pointer register.
Base class for machine instructions.
BaseSemantics::SValuePtr readAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *, size_t valueNBits)
Reads from a memory address and updates a register with the effective address that was read...
virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE
Returns the function call return address register.
Main namespace for the ROSE library.
void regcache_init()
Load the cached register descriptors.
virtual const RegisterDictionary * get_register_dictionary() const
Access the register dictionary.
void memory_init()
Make sure memory is set up correctly.
virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE
Access the register dictionary.
boost::shared_ptr< class Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE
Returns the instruction pointer register.
Base classes for instruction semantics.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0, const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE
Virtual constructor.
Describes (part of) a physical CPU register.
size_t addressWidth() const
Property: Width of memory addresses.
boost::shared_ptr< class RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
boost::shared_ptr< class DispatcherPowerpc > DispatcherPowerpcPtr
Shared-ownership pointer to a PowerPC instruction dispatcher.
virtual int iproc_key(SgAsmInstruction *insn_) const ROSE_OVERRIDE
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
Represents one PowerPC machine instruction.
Rose::BinaryAnalysis::PowerpcInstructionKind get_kind() const
Property: Instruction kind.
void iproc_init()
Loads the iproc table with instruction processing functors.
Base class for most instruction semantics RISC operators.
const RegisterDictionary * regdict
See set_register_dictionary().
Base class for expressions.
void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow)
Set the XER OV and SO bits as specified.
static DispatcherPowerpcPtr instance()
Construct a prototypical dispatcher.
static DispatcherPowerpcPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
Defines registers available for a particular architecture.
Definition: Registers.h:35
static DispatcherPowerpcPtr instance(size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
virtual void updateCr0(const BaseSemantics::SValuePtr &result)
Write status flags for result.
static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &d)
Dynamic cast to a DispatcherPowerpcPtr with assertion.
void writeAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *destination, const BaseSemantics::SValuePtr &value)
Writes a value to a memory address and updates a register with the effective address to which the val...