ROSE  0.11.51.0
DispatcherPowerpc.h
1 // Semantics for 32-bit Motorola-IBM PowerPC microprocessors using ROSE instruction semantics API2
2 // This code was derived from $ROSE/projects/assemblyToSourceAst/powerpcInstructionSemantics.h,
3 // which is mostly a copy of $ROSE/projects/SemanticSignatureVectors/powerpcInstructionSemantics.h
4 //
5 // The ROSE style guide indicates that PowerPC, when used as part of a symbol in ROSE source code,
6 // should be capitalized as "Powerpc" (e.g., "DispatcherPowerpc", the same rule that consistently
7 // capitializes x86 as "DispatcherX86").
8 #ifndef ROSE_BinaryAnalysis_InstructionSemantics2_DispatcherPowerpc_H
9 #define ROSE_BinaryAnalysis_InstructionSemantics2_DispatcherPowerpc_H
10 #include <featureTests.h>
11 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
12 
13 #include <Rose/BinaryAnalysis/InstructionSemantics2/BaseSemantics.h>
14 
15 #include <boost/serialization/access.hpp>
16 #include <boost/serialization/base_object.hpp>
17 #include <boost/serialization/export.hpp>
18 #include <boost/serialization/split_member.hpp>
19 
20 namespace Rose {
21 namespace BinaryAnalysis {
22 namespace InstructionSemantics2 {
23 
25 typedef boost::shared_ptr<class DispatcherPowerpc> DispatcherPowerpcPtr;
26 
28 public:
31 
34 
45 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
46 private:
47  friend class boost::serialization::access;
48 
49  template<class S>
50  void save(S &s, const unsigned /*version*/) const {
51  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
52  }
53 
54  template<class S>
55  void load(S &s, const unsigned /*version*/) {
56  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
57  regcache_init();
58  iproc_init();
59  memory_init();
60  }
61 
62  BOOST_SERIALIZATION_SPLIT_MEMBER();
63 #endif
64 
65 protected:
66  // Prototypical constructor
67  DispatcherPowerpc(): BaseSemantics::Dispatcher(32, RegisterDictionary::dictionary_powerpc32()) {}
68 
69  // Prototypical constructor
70  DispatcherPowerpc(size_t addrWidth, const RegisterDictionary *regs/*=NULL*/)
71  : BaseSemantics::Dispatcher(addrWidth, regs ? regs : SgAsmPowerpcInstruction::registersForWidth(addrWidth)) {}
72 
73  DispatcherPowerpc(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
74  : BaseSemantics::Dispatcher(ops, addrWidth, regs ? regs : SgAsmPowerpcInstruction::registersForWidth(addrWidth)) {
75  ASSERT_require(32==addrWidth || 64==addrWidth);
76  regcache_init();
77  iproc_init();
78  memory_init();
79  initializeState(ops->currentState());
80  }
81 
83  void iproc_init();
84 
88  void regcache_init();
89 
91  void memory_init();
92 
93 public:
96  static DispatcherPowerpcPtr instance() {
98  }
99 
101  static DispatcherPowerpcPtr instance(size_t addrWidth, const RegisterDictionary *regs = NULL) {
102  return DispatcherPowerpcPtr(new DispatcherPowerpc(addrWidth, regs));
103  }
104 
106  static DispatcherPowerpcPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth,
107  const RegisterDictionary *regs=NULL) {
108  return DispatcherPowerpcPtr(new DispatcherPowerpc(ops, addrWidth, regs));
109  }
110 
113  const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE {
114  if (0==addrWidth)
115  addrWidth = addressWidth();
116  if (!regs)
117  regs = registerDictionary();
118  return instance(ops, addrWidth, regs);
119  }
120 
122  static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &d) {
123  DispatcherPowerpcPtr retval = boost::dynamic_pointer_cast<DispatcherPowerpc>(d);
124  assert(retval!=NULL);
125  return retval;
126  }
127 
128  virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE;
129 
130  virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE;
131  virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE;
132  virtual RegisterDescriptor stackFrameRegister() const ROSE_OVERRIDE;
133  virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE;
134 
135  virtual int iprocKey(SgAsmInstruction *insn_) const ROSE_OVERRIDE {
136  SgAsmPowerpcInstruction *insn = isSgAsmPowerpcInstruction(insn_);
137  assert(insn!=NULL);
138  return insn->get_kind();
139  }
140 
145  void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow);
146 
148  virtual void updateCr0(const BaseSemantics::SValuePtr &result);
149 
153 
158 };
159 
160 } // namespace
161 } // namespace
162 } // namespace
163 
164 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
166 #endif
167 
168 #endif
169 #endif
const RegisterDictionary * registerDictionary() const
Property: Register dictionary.
Definition: Dispatcher.h:195
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
virtual void initializeState(const StatePtr &)
Initialize the state.
virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE
Returns the stack pointer register.
Base class for machine instructions.
virtual RegisterDescriptor stackFrameRegister() const ROSE_OVERRIDE
Returns the stack call frame register.
BaseSemantics::SValuePtr readAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *, size_t valueNBits)
Reads from a memory address and updates a register with the effective address that was read...
virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE
Returns the function call return address register.
Main namespace for the ROSE library.
void regcache_init()
Load the cached register descriptors.
void memory_init()
Make sure memory is set up correctly.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE
Returns the instruction pointer register.
virtual int iprocKey(SgAsmInstruction *insn_) const ROSE_OVERRIDE
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
Base classes for instruction semantics.
Definition: Dispatcher.h:18
DispatcherPowerpcPtr Ptr
Shared-ownership pointer.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0, const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE
Virtual constructor.
Describes (part of) a physical CPU register.
size_t addressWidth() const
Property: Width of memory addresses.
Definition: Dispatcher.h:225
boost::shared_ptr< class DispatcherPowerpc > DispatcherPowerpcPtr
Shared-ownership pointer to a PowerPC instruction dispatcher.
Represents one PowerPC machine instruction.
Rose::BinaryAnalysis::PowerpcInstructionKind get_kind() const
Property: Instruction kind.
void iproc_init()
Loads the iproc table with instruction processing functors.
Base class for most instruction semantics RISC operators.
Definition: RiscOperators.h:48
const RegisterDictionary * regdict
See registerDictionary property.
Definition: Dispatcher.h:53
Base class for expressions.
Dispatches instructions through the RISC layer.
Definition: Dispatcher.h:44
void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow)
Set the XER OV and SO bits as specified.
static DispatcherPowerpcPtr instance()
Construct a prototypical dispatcher.
static DispatcherPowerpcPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
Defines registers available for a particular architecture.
Definition: Registers.h:37
static DispatcherPowerpcPtr instance(size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
virtual void updateCr0(const BaseSemantics::SValuePtr &result)
Write status flags for result.
static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &d)
Dynamic cast to a DispatcherPowerpcPtr with assertion.
void writeAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *destination, const BaseSemantics::SValuePtr &value)
Writes a value to a memory address and updates a register with the effective address to which the val...