8#ifndef ROSE_BinaryAnalysis_InstructionSemantics_DispatcherPowerpc_H 
    9#define ROSE_BinaryAnalysis_InstructionSemantics_DispatcherPowerpc_H 
   10#include <featureTests.h> 
   11#ifdef ROSE_ENABLE_BINARY_ANALYSIS 
   13#include <Rose/BinaryAnalysis/BasicTypes.h> 
   14#include <Rose/BinaryAnalysis/InstructionSemantics/BaseSemantics.h> 
   16#ifdef ROSE_ENABLE_BOOST_SERIALIZATION 
   17#include <boost/serialization/access.hpp> 
   18#include <boost/serialization/base_object.hpp> 
   19#include <boost/serialization/export.hpp> 
   20#include <boost/serialization/split_member.hpp> 
   24namespace BinaryAnalysis {
 
   25namespace InstructionSemantics {
 
   48#ifdef ROSE_ENABLE_BOOST_SERIALIZATION 
   50    friend class boost::serialization::access;
 
   53    void save(S &s, 
const unsigned )
 const {
 
   54        s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(
Super);
 
   58    void load(S &s, 
const unsigned ) {
 
   59        s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(
Super);
 
   65    BOOST_SERIALIZATION_SPLIT_MEMBER();
 
 
  138#ifdef ROSE_ENABLE_BOOST_SERIALIZATION 
Dispatches instructions through the RISC layer.
 
Base class for most instruction semantics RISC operators.
 
RegisterDescriptor REG_CTR
Cached register.
 
BaseSemantics::Dispatcher Super
Base type.
 
static DispatcherPowerpcPtr instance(const Architecture::BaseConstPtr &, const BaseSemantics::RiscOperatorsPtr &)
Constructor.
 
void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow)
Set the XER OV and SO bits as specified.
 
RegisterDescriptor REG_CR0_LT
Cached register.
 
void writeAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *destination, const BaseSemantics::SValuePtr &value)
Writes a value to a memory address and updates a register with the effective address to which the val...
 
RegisterDescriptor REG_CR0
Cached register.
 
RegisterDescriptor REG_IAR
Cached register.
 
RegisterDescriptor REG_XER_CA
Cached register.
 
virtual RegisterDescriptor instructionPointerRegister() const override
Returns the instruction pointer register.
 
RegisterDescriptor REG_XER_OV
Cached register.
 
virtual void updateCr0(const BaseSemantics::SValuePtr &result)
Write status flags for result.
 
virtual RegisterDescriptor callReturnRegister() const override
Returns the function call return address register.
 
DispatcherPowerpcPtr Ptr
Shared-ownership pointer.
 
RegisterDescriptor REG_CR
Cached register.
 
RegisterDescriptor REG_XER
Cached register.
 
RegisterDescriptor REG_XER_SO
Cached register.
 
virtual int iprocKey(SgAsmInstruction *insn_) const override
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table.
 
static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &)
Dynamic cast to a DispatcherPowerpcPtr with assertion.
 
BaseSemantics::SValuePtr readAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *, size_t valueNBits)
Reads from a memory address and updates a register with the effective address that was read.
 
static DispatcherPowerpcPtr instance(const Architecture::BaseConstPtr &)
Construct a prototypical dispatcher.
 
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &) const override
Virtual constructor.
 
RegisterDescriptor REG_LR
Cached register.
 
Describes (part of) a physical CPU register.
 
Base class for expressions.
 
Base class for machine instructions.
 
std::shared_ptr< const Base > BaseConstPtr
Reference counted pointer for Architecture::Base.
 
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
 
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
 
boost::shared_ptr< class DispatcherPowerpc > DispatcherPowerpcPtr
Shared-ownership pointer to a PowerPC instruction dispatcher.