ROSE  0.11.2.0
DispatcherPowerpc.h
1 // Semantics for 32-bit Motorola-IBM PowerPC microprocessors using ROSE instruction semantics API2
2 // This code was derived from $ROSE/projects/assemblyToSourceAst/powerpcInstructionSemantics.h,
3 // which is mostly a copy of $ROSE/projects/SemanticSignatureVectors/powerpcInstructionSemantics.h
4 //
5 // The ROSE style guide indicates that PowerPC, when used as part of a symbol in ROSE source code,
6 // should be capitalized as "Powerpc" (e.g., "DispatcherPowerpc", the same rule that consistently
7 // capitializes x86 as "DispatcherX86").
8 #ifndef ROSE_DispatcherPpc_H
9 #define ROSE_DispatcherPpc_H
10 #include <rosePublicConfig.h>
11 #ifdef ROSE_BUILD_BINARY_ANALYSIS_SUPPORT
12 
13 #include "BaseSemantics2.h"
14 
15 #include <boost/serialization/access.hpp>
16 #include <boost/serialization/base_object.hpp>
17 #include <boost/serialization/export.hpp>
18 #include <boost/serialization/split_member.hpp>
19 
20 namespace Rose {
21 namespace BinaryAnalysis {
22 namespace InstructionSemantics2 {
23 
25 typedef boost::shared_ptr<class DispatcherPowerpc> DispatcherPowerpcPtr;
26 
28 public:
30 
38 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
39 private:
40  friend class boost::serialization::access;
41 
42  template<class S>
43  void save(S &s, const unsigned /*version*/) const {
44  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
45  }
46 
47  template<class S>
48  void load(S &s, const unsigned /*version*/) {
49  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
50  regcache_init();
51  iproc_init();
52  memory_init();
53  }
54 
55  BOOST_SERIALIZATION_SPLIT_MEMBER();
56 #endif
57 
58 protected:
59  // Prototypical constructor
60  DispatcherPowerpc(): BaseSemantics::Dispatcher(32, RegisterDictionary::dictionary_powerpc32()) {}
61 
62  // Prototypical constructor
63  DispatcherPowerpc(size_t addrWidth, const RegisterDictionary *regs/*=NULL*/)
64  : BaseSemantics::Dispatcher(addrWidth, regs ? regs : SgAsmPowerpcInstruction::registersForWidth(addrWidth)) {}
65 
66  DispatcherPowerpc(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
67  : BaseSemantics::Dispatcher(ops, addrWidth, regs ? regs : SgAsmPowerpcInstruction::registersForWidth(addrWidth)) {
68  ASSERT_require(32==addrWidth || 64==addrWidth);
69  regcache_init();
70  iproc_init();
71  memory_init();
72  }
73 
75  void iproc_init();
76 
78  void regcache_init();
79 
81  void memory_init();
82 
83 public:
86  static DispatcherPowerpcPtr instance() {
88  }
89 
91  static DispatcherPowerpcPtr instance(size_t addrWidth, const RegisterDictionary *regs = NULL) {
92  return DispatcherPowerpcPtr(new DispatcherPowerpc(addrWidth, regs));
93  }
94 
96  static DispatcherPowerpcPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth,
97  const RegisterDictionary *regs=NULL) {
98  return DispatcherPowerpcPtr(new DispatcherPowerpc(ops, addrWidth, regs));
99  }
100 
103  const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE {
104  if (0==addrWidth)
105  addrWidth = addressWidth();
106  if (!regs)
107  regs = get_register_dictionary();
108  return instance(ops, addrWidth, regs);
109  }
110 
112  static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &d) {
113  DispatcherPowerpcPtr retval = boost::dynamic_pointer_cast<DispatcherPowerpc>(d);
114  assert(retval!=NULL);
115  return retval;
116  }
117 
118  virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE;
119 
120  virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE;
121  virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE;
122  virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE;
123 
124  virtual int iproc_key(SgAsmInstruction *insn_) const ROSE_OVERRIDE {
125  SgAsmPowerpcInstruction *insn = isSgAsmPowerpcInstruction(insn_);
126  assert(insn!=NULL);
127  return insn->get_kind();
128  }
129 
134  void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow);
135 
137  virtual void updateCr0(const BaseSemantics::SValuePtr &result);
138 
142 
147 };
148 
149 } // namespace
150 } // namespace
151 } // namespace
152 
153 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
155 #endif
156 
157 #endif
158 #endif
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE
Returns the stack pointer register.
Base class for machine instructions.
BaseSemantics::SValuePtr readAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *, size_t valueNBits)
Reads from a memory address and updates a register with the effective address that was read...
virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE
Returns the function call return address register.
Main namespace for the ROSE library.
void regcache_init()
Load the cached register descriptors.
virtual const RegisterDictionary * get_register_dictionary() const
Access the register dictionary.
void memory_init()
Make sure memory is set up correctly.
virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE
Access the register dictionary.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE
Returns the instruction pointer register.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0, const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE
Virtual constructor.
Describes (part of) a physical CPU register.
size_t addressWidth() const
Property: Width of memory addresses.
boost::shared_ptr< class DispatcherPowerpc > DispatcherPowerpcPtr
Shared-ownership pointer to a PowerPC instruction dispatcher.
virtual int iproc_key(SgAsmInstruction *insn_) const ROSE_OVERRIDE
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
Represents one PowerPC machine instruction.
Rose::BinaryAnalysis::PowerpcInstructionKind get_kind() const
Property: Instruction kind.
void iproc_init()
Loads the iproc table with instruction processing functors.
Base class for most instruction semantics RISC operators.
const RegisterDictionary * regdict
See set_register_dictionary().
Base class for expressions.
void setXerOverflow(const BaseSemantics::SValuePtr &hadOverflow)
Set the XER OV and SO bits as specified.
static DispatcherPowerpcPtr instance()
Construct a prototypical dispatcher.
static DispatcherPowerpcPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
Defines registers available for a particular architecture.
Definition: Registers.h:38
static DispatcherPowerpcPtr instance(size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
virtual void updateCr0(const BaseSemantics::SValuePtr &result)
Write status flags for result.
static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &d)
Dynamic cast to a DispatcherPowerpcPtr with assertion.
void writeAndUpdate(BaseSemantics::RiscOperators *, SgAsmExpression *destination, const BaseSemantics::SValuePtr &value)
Writes a value to a memory address and updates a register with the effective address to which the val...