Description
Architecture-specific information for PowerPC with 32-bit word size.
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PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple–IBM–Motorola alliance, known as AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors.
PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform (CHRP) initiatives in the 1990s. Originally intended for personal computers, the architecture is well known for being used by Apple's Power Macintosh, PowerBook, iMac, iBook, eMac, Mac Mini, and Xserve lines from 1994 until 2006, when Apple migrated to Intel's x86. It has since become a niche in personal computers, but remains popular for embedded and high-performance processors. Its use in the 7th generation of video game consoles and embedded applications provide an array of uses, including satellites, and the Curiosity and Perseverance rovers on Mars. In addition, PowerPC CPUs are still used in AmigaOne and third party AmigaOS 4 personal computers.
PowerPC is largely based on the earlier IBM POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation; newer chips in the Power series use the Power ISA.
Definition at line 28 of file Powerpc32.h.
#include <Rose/BinaryAnalysis/Architecture/Powerpc32.h>
Public Types | |
| using | Ptr = Powerpc32Ptr |
 Public Types inherited from Rose::BinaryAnalysis::Architecture::Powerpc | |
| using | Ptr = PowerpcPtr |
| Public Types inherited from Rose::BinaryAnalysis::Architecture::Base | |
| using | Ptr = BasePtr |
| Reference counting pointer. | |
| using | ConstPtr = BaseConstPtr |
| Reference counting pointer to const object. | |
Public Member Functions | |
| RegisterDictionary::Ptr | registerDictionary () const override |
| Property: Register dictionary. | |
| bool | matchesHeader (SgAsmGenericHeader *) const override |
| Tests whether this architecture matches a file header. | |
| Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::Powerpc | |
| virtual const CallingConvention::Dictionary & | callingConventions () const override |
| Property: Calling convention definitions. | |
| std::string | instructionMnemonic (const SgAsmInstruction *) const override |
| Mnemonic for an instruction. | |
| std::string | instructionDescription (const SgAsmInstruction *) const override |
| Description for an instruction. | |
| Sawyer::Container::Interval< size_t > | bytesPerInstruction () const override |
| Valid sizes for encoded machine instructions. | |
| Alignment | instructionAlignment () const override |
| Alignment for encoded machine instructions. | |
| bool | terminatesBasicBlock (SgAsmInstruction *) const override |
| Determines whether the specified instruction normally terminates a basic block. | |
| bool | isUnknown (const SgAsmInstruction *) const override |
| Returns true if the instruction is the special "unknown" instruction. | |
| bool | isFunctionCallFast (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const override |
| Returns true if the specified basic block looks like a function call. | |
| bool | isFunctionReturnFast (const std::vector< SgAsmInstruction * > &) const override |
| Returns true if the specified basic block looks like a function return. | |
| AddressSet | getSuccessors (SgAsmInstruction *, bool &complete) const override |
| Control flow successors for a single instruction. | |
| Disassembler::BasePtr | newInstructionDecoder () const override |
| Construct and return a new instruction decoder. | |
| Unparser::BasePtr | newUnparser () const override |
| Construct and return a new instruction unparser. | |
| virtual InstructionSemantics::BaseSemantics::DispatcherPtr | newInstructionDispatcher (const InstructionSemantics::BaseSemantics::RiscOperatorsPtr &) const override |
| Construct and return a new instruction dispatcher. | |
| std::vector< Partitioner2::FunctionPrologueMatcherPtr > | functionPrologueMatchers (const Partitioner2::EnginePtr &) const override |
| Instruction patterns matching function prologues. | |
| Public Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base | |
| const std::string & | name () const |
| Property: Architecture definition name. | |
| ByteOrder::Endianness | byteOrder () const |
| Property: Byte order for memory. | |
| virtual RegisterDictionaryPtr | interruptDictionary () const |
| Property: Interrupt dictionary. | |
| virtual bool | matchesName (const std::string &) const |
| Tests whether this architecture matches a name. | |
| bool | instructionsCanOverlap () const |
| Whether instructions can overlap in memory. | |
| virtual std::string | toString (const SgAsmExpression *) const |
| Unparse an expression to a string. | |
| virtual bool | isControlTransfer (const SgAsmInstruction *) const |
| Returns true if the specified instruction is a control transfer instruction. | |
| virtual Sawyer::Optional< rose_addr_t > | branchTarget (SgAsmInstruction *) const |
| Obtains the virtual address for a branching instruction. | |
| virtual std::vector< Partitioner2::BasicBlockCallbackPtr > | basicBlockCreationHooks (const Partitioner2::EnginePtr &) const |
| Architecture-specific basic block callbacks for partitioning. | |
| const Sawyer::Optional< size_t > & | registrationId () const |
| Property: Registration identification number. | |
| void | registrationId (const Sawyer::Optional< size_t > &) |
| Property: Registration identification number. | |
| size_t | bytesPerWord () const |
| Property: Word size. | |
| size_t | bitsPerWord () const |
| Property: Word size. | |
| virtual Unparser::BasePtr | newInstructionUnparser () const |
| Construct and return a new instruction unparser. | |
| virtual std::string | toString (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual std::string | toStringNoAddr (const SgAsmInstruction *) const |
| Unparse an instruction to a string. | |
| virtual bool | isFunctionCallSlow (const std::vector< SgAsmInstruction * > &, rose_addr_t *target, rose_addr_t *ret) const |
| Returns true if the specified basic block looks like a function call. | |
| virtual bool | isFunctionReturnSlow (const std::vector< SgAsmInstruction * > &) const |
| Returns true if the specified basic block looks like a function return. | |
| AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete) const |
| Control flow successors for a basic block. | |
| virtual AddressSet | getSuccessors (const std::vector< SgAsmInstruction * > &basicBlock, bool &complete, const MemoryMapPtr &initial_memory) const |
| Control flow successors for a basic block. | |
Static Public Member Functions | |
| static Ptr | instance (ByteOrder::Endianness) |
| Allocating constructor. | |
Protected Member Functions | |
| Powerpc32 (ByteOrder::Endianness) | |
| Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::Powerpc | |
| Powerpc (size_t bytesPerWord, ByteOrder::Endianness) | |
| CallingConvention::DefinitionPtr | cc_ibm (size_t bitsPerWord) const |
| Protected Member Functions inherited from Rose::BinaryAnalysis::Architecture::Base | |
| Base (const std::string &name, size_t bytesPerWord, ByteOrder::Endianness byteOrder) | |
| Ptr | ptr () |
| ConstPtr | constPtr () const |
| virtual Unparser::BasePtr | insnUnparser () const |
Additional Inherited Members | |
| Protected Attributes inherited from Rose::BinaryAnalysis::Architecture::Base | |
| Sawyer::Cached< RegisterDictionaryPtr > | registerDictionary_ |
| Sawyer::Cached< RegisterDictionaryPtr > | interruptDictionary_ |
| Sawyer::Cached< CallingConvention::Dictionary > | callingConventions_ |
| Sawyer::Cached< Unparser::Base::Ptr > | insnToString_ |
| Sawyer::Cached< Unparser::Base::Ptr > | insnToStringNoAddr_ |
Member Typedef Documentation
◆ Ptr
| using Rose::BinaryAnalysis::Architecture::Powerpc32::Ptr = Powerpc32Ptr |
Definition at line 30 of file Powerpc32.h.
Member Function Documentation
◆ registerDictionary()
|
overridevirtual |
Property: Register dictionary.
The register dictionary defines a mapping between register names and register descriptors (RegisterDescriptor), and thus how the registers map into hardware.
Since dictionaries are generally not modified, it is permissible for this function to return the same dictionary every time it's called. The dictionary can be constructed on the first call.
Thread safety: Thread safe.
Implements Rose::BinaryAnalysis::Architecture::Base.
◆ matchesHeader()
|
overridevirtual |
Tests whether this architecture matches a file header.
Returns true if this architecture matches the specified file header, and false otherwise.
The default implementation always returns false.
Reimplemented from Rose::BinaryAnalysis::Architecture::Base.
The documentation for this class was generated from the following file:
