ROSE 0.11.145.147
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Semantically evaluates Intel x86 instructions.
Definition at line 31 of file DispatcherX86.h.
#include <Rose/BinaryAnalysis/InstructionSemantics/DispatcherX86.h>
Public Types | |
enum | AccessMode { READ_REGISTER , PEEK_REGISTER } |
using | Super = BaseSemantics::Dispatcher |
Base type. | |
using | Ptr = DispatcherX86Ptr |
Shared-ownership pointer. | |
Public Types inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher | |
using | Ptr = DispatcherPtr |
Shared-ownership pointer. | |
Public Member Functions | |
void | iproc_init () |
Loads the iproc table with instruction processing functors. | |
void | regcache_init () |
Load the cached register descriptors. | |
void | memory_init () |
Make sure memory properties are set up correctly. | |
virtual BaseSemantics::DispatcherPtr | create (const BaseSemantics::RiscOperatorsPtr &) const override |
Virtual constructor. | |
virtual RegisterDictionary::RegisterDescriptors | get_usual_registers () const |
Get list of common registers. | |
virtual RegisterDescriptor | instructionPointerRegister () const override |
Returns the instruction pointer register. | |
virtual RegisterDescriptor | stackPointerRegister () const override |
Returns the stack pointer register. | |
virtual RegisterDescriptor | stackFrameRegister () const override |
Returns the stack call frame register. | |
virtual RegisterDescriptor | callReturnRegister () const override |
Returns the function call return address register. | |
virtual int | iprocKey (SgAsmInstruction *insn_) const override |
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table. | |
virtual void | write (SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) override |
Writes to an L-value expression. | |
virtual void | initializeState (const BaseSemantics::StatePtr &) override |
Initialize the state. | |
virtual BaseSemantics::SValuePtr | readRegister (RegisterDescriptor, AccessMode mode=READ_REGISTER) |
Architecture-specific read from register. | |
virtual void | writeRegister (RegisterDescriptor, const BaseSemantics::SValuePtr &result) |
Architecture-specific write to register. | |
virtual void | setFlagsForResult (const BaseSemantics::SValuePtr &result) |
Set parity, sign, and zero flags appropriate for result value. | |
virtual void | setFlagsForResult (const BaseSemantics::SValuePtr &result, const BaseSemantics::SValuePtr &cond) |
Conditionally set parity, sign, and zero flags appropriate for result value. | |
virtual BaseSemantics::SValuePtr | parity (const BaseSemantics::SValuePtr &v) |
Returns true if byte v has an even number of bits set; false for an odd number. | |
virtual BaseSemantics::SValuePtr | invertMaybe (const BaseSemantics::SValuePtr &value, bool maybe) |
Conditionally invert the bits of value . | |
virtual BaseSemantics::SValuePtr | greaterOrEqualToTen (const BaseSemantics::SValuePtr &value) |
Determines whether value is greater than or equal to ten. | |
virtual BaseSemantics::SValuePtr | flagsCombo (X86InstructionKind k) |
Return a Boolean for the specified flag combo for an instruction. | |
virtual BaseSemantics::SValuePtr | repEnter (X86RepeatPrefix) |
Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction. | |
virtual void | repLeave (X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag) |
Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction. | |
virtual BaseSemantics::SValuePtr | doIncOperation (const BaseSemantics::SValuePtr &a, bool dec, bool setCarry) |
Increments or decrements a value and adjusts flags. | |
virtual BaseSemantics::SValuePtr | doRotateOperation (X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &total_rotate, size_t rotateSignificantBits) |
Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes. | |
virtual BaseSemantics::SValuePtr | doShiftOperation (X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &source_bits, const BaseSemantics::SValuePtr &total_shift, size_t shiftSignificantBits) |
Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes. | |
virtual void | pushFloatingPoint (const BaseSemantics::SValuePtr &valueToPush) |
Push floating-point value onto FP stack. | |
virtual BaseSemantics::SValuePtr | readFloatingPointStack (size_t position) |
Read a value from the floating point stack. | |
virtual void | popFloatingPoint () |
Pop the top item from the floating point stack. | |
virtual BaseSemantics::SValuePtr | fixMemoryAddress (const BaseSemantics::SValuePtr &address) const |
Extend or truncate value to propert memory address width. | |
virtual BaseSemantics::SValuePtr | saturateSignedToUnsigned (const BaseSemantics::SValuePtr &, size_t narrowerWidth) |
Convert a signed value to a narrower unsigned type. | |
virtual BaseSemantics::SValuePtr | saturateSignedToSigned (const BaseSemantics::SValuePtr &, size_t narrowerWidth) |
Convert a signed value to a narrower signed type. | |
virtual BaseSemantics::SValuePtr | saturateUnsignedToUnsigned (const BaseSemantics::SValuePtr &, size_t narrowerWidth) |
Convert an unsigned value to a narrower unsigned type. | |
X86InstructionSize | processorMode () const |
CPU mode of operation. | |
void | processorMode (X86InstructionSize m) |
CPU mode of operation. | |
virtual BaseSemantics::SValuePtr | doAddOperation (BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn) |
Adds two values and adjusts flags. | |
virtual BaseSemantics::SValuePtr | doAddOperation (BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn, const BaseSemantics::SValuePtr &cond) |
Adds two values and adjusts flags. | |
Public Member Functions inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher | |
virtual void | processInstruction (SgAsmInstruction *insn) |
Process a single instruction. | |
virtual InsnProcessor * | iprocLookup (SgAsmInstruction *insn) |
Lookup the processor for an instruction. | |
virtual void | iprocReplace (SgAsmInstruction *insn, InsnProcessor *iproc) |
Replace an instruction processor with another. | |
virtual void | iprocSet (int key, InsnProcessor *iproc) |
Set an iproc table entry to the specified value. | |
virtual InsnProcessor * | iprocGet (int key) |
Obtain an iproc table entry for the specified key. | |
Architecture::BaseConstPtr | architecture () const |
Property: Architecture. | |
virtual StatePtr | currentState () const |
Get a pointer to the state object. | |
virtual SValuePtr | protoval () const |
Return the prototypical value. | |
virtual SgAsmInstruction * | currentInstruction () const |
Returns the instruction that is being processed. | |
virtual SValuePtr | number_ (size_t nbits, uint64_t number) const |
Return a semantic value representing a number. | |
RegisterDictionaryPtr | registerDictionary () const |
Property: Register dictionary. | |
virtual RegisterDescriptor | findRegister (const std::string ®name, size_t nbits=0, bool allowMissing=false) const |
Lookup a register by name. | |
size_t | addressWidth () const |
Property: Width of memory addresses in bits. | |
virtual void | advanceInstructionPointer (SgAsmInstruction *) |
Update the instruction pointer register. | |
virtual RegisterDescriptor | segmentRegister (SgAsmMemoryReferenceExpression *) |
Returns a register descriptor for the segment part of a memory reference expression. | |
virtual void | incrementRegisters (SgAsmExpression *) |
Increment all auto-increment registers in the expression. | |
virtual void | decrementRegisters (SgAsmExpression *) |
Decrement all auto-decrement registers in the expression. | |
virtual void | preUpdate (SgAsmExpression *, const BaseSemantics::SValuePtr &enabled) |
Update registers for pre-add expressions. | |
virtual void | postUpdate (SgAsmExpression *, const BaseSemantics::SValuePtr &enabled) |
Update registers for post-add expressions. | |
virtual SValuePtr | effectiveAddress (SgAsmExpression *, size_t nbits=0) |
Returns a memory address by evaluating the address expression. | |
virtual SValuePtr | read (SgAsmExpression *, size_t value_nbits=0, size_t addr_nbits=0) |
Reads an R-value expression. | |
virtual RiscOperatorsPtr | operators () const |
Property: RISC operators. | |
virtual void | operators (const RiscOperatorsPtr &) |
Property: RISC operators. | |
virtual SValuePtr | undefined_ (size_t nbits) const |
Return a new undefined semantic value. | |
virtual SValuePtr | unspecified_ (size_t nbits) const |
Return a new undefined semantic value. | |
bool | autoResetInstructionPointer () const |
Property: Reset instruction pointer register for each instruction. | |
void | autoResetInstructionPointer (bool b) |
Property: Reset instruction pointer register for each instruction. | |
Static Public Member Functions | |
static DispatcherX86Ptr | instance (const Architecture::BaseConstPtr &) |
Construct a prototypical dispatcher. | |
static DispatcherX86Ptr | instance (const Architecture::BaseConstPtr &, const BaseSemantics::RiscOperatorsPtr &) |
Constructor. | |
static DispatcherX86Ptr | promote (const BaseSemantics::DispatcherPtr &) |
Dynamic cast to a DispatcherX86Ptr with assertion. | |
Protected Member Functions | |
DispatcherX86 (const Architecture::BaseConstPtr &) | |
DispatcherX86 (const Architecture::BaseConstPtr &, const BaseSemantics::RiscOperatorsPtr &) | |
Protected Member Functions inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher | |
Dispatcher (const Architecture::BaseConstPtr &) | |
Dispatcher (const Architecture::BaseConstPtr &, const RiscOperatorsPtr &) | |
Protected Attributes | |
X86InstructionSize | processorMode_ |
Protected Attributes inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher | |
bool | autoResetInstructionPointer_ = true |
Reset instruction pointer register for each instruction. | |
InsnProcessors | iproc_table |
Additional Inherited Members | |
Protected Types inherited from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher | |
typedef std::vector< InsnProcessor * > | InsnProcessors |
Base type.
Definition at line 34 of file DispatcherX86.h.
Shared-ownership pointer.
Definition at line 37 of file DispatcherX86.h.
enum Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::AccessMode |
Definition at line 158 of file DispatcherX86.h.
void Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::iproc_init | ( | ) |
Loads the iproc table with instruction processing functors.
This normally happens from the constructor.
void Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::regcache_init | ( | ) |
Load the cached register descriptors.
This happens at construction and when the registerDictionary property is changed.
void Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::memory_init | ( | ) |
Make sure memory properties are set up correctly.
For instance, byte order should be little endian.
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static |
Construct a prototypical dispatcher.
The only thing this dispatcher can be used for is to create another dispatcher with the virtual create method.
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overridevirtual |
Virtual constructor.
Implements Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.
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inline |
CPU mode of operation.
Definition at line 142 of file DispatcherX86.h.
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inline |
CPU mode of operation.
Definition at line 143 of file DispatcherX86.h.
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virtual |
Get list of common registers.
Returns a list of non-overlapping registers composed of the largest registers except using individual flags for the fields of the FLAGS/EFLAGS register.
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overridevirtual |
Returns the instruction pointer register.
Reimplemented from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.
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overridevirtual |
Returns the stack pointer register.
Reimplemented from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.
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overridevirtual |
Returns the stack call frame register.
Reimplemented from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.
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overridevirtual |
Returns the function call return address register.
Reimplemented from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.
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overridevirtual |
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table.
Implements Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.
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overridevirtual |
Writes to an L-value expression.
The expression can be a register or memory reference. The width of the address passed to lower-level memory access functions is specified by addr_nbits
. If addr_nbits
is zero then the natural width of the effective address is passed to lower level functions.
Reimplemented from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.
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overridevirtual |
Initialize the state.
Some architectures benefit from having their initial state initialized in a certain way. For instance, on x86/amd64 the segment registers CS, DS, and SS typically refer to the entire machine memory and can be initialized to have a zero base address.
Reimplemented from Rose::BinaryAnalysis::InstructionSemantics::BaseSemantics::Dispatcher.
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virtual |
Architecture-specific read from register.
Similar to RiscOperators::readRegister, but might do additional architecture-specific things.
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virtual |
Architecture-specific write to register.
Similar to RiscOperators::writeRegister, but might do additional architecture-specific things. For instance, writing to a 32-bit GPR such as "eax" on x86-64 will write zeros to the upper half of "rax".
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virtual |
Conditionally invert the bits of value
.
The bits are inverted if maybe
is true, otherwise value
is returned.
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virtual |
Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction.
The return value is true if ECX is non-zero or the instruction doesn't have repeat prefix, and false otherwise. Use this in conjunction with repLeave().
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virtual |
Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction.
The in_loop
argument is the Boolean that indicates whether we just executed the instruction, and is usually the return value from the previous repEnter() call. If in_loop
is false then this function is a no-op. Otherwise, the ECX register is decremented and, if it is non-zero and the repeat condition (true, equal, or not-equal) is satisified, then the EIP register is reset to the specified instruction address causing the instruction to be repeated. Use this in conjunction with repEnter(). The REP and REPE prefixes are shared, both represented by x86_repeat_repe, and we use the honorZeroFlag to decide whether the prefix is REP (false) or REPE (true).
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virtual |
Adds two values and adjusts flags.
This method can be used for subtraction if b
is two's complement and invertCarries
is set. If cond
is supplied, then the addition and flag adjustments are conditional.
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virtual |
Adds two values and adjusts flags.
This method can be used for subtraction if b
is two's complement and invertCarries
is set. If cond
is supplied, then the addition and flag adjustments are conditional.
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virtual |
Increments or decrements a value and adjusts flags.
If dec
is set then the value is decremented instead of incremented. If setCarry
is set then the CF flag is affected.
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virtual |
Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes.
The rotate amount is always 8 bits wide in the instruction, but the semantics mask off all but the low-order bits, keeping 5 bits in 32-bit mode and 6 bits in 64-bit mode (indicated by the rotateSignificantBits argument).
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virtual |
Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes.
The shift amount is always 8 bits wide in the instruction, but the semantics mask off all but the low-order bits, keeping 5 bits in 32-bit mode and 7 bits in 64-bit mode (indicated by the shiftSignificantBits
argument). The semantics of SHL and SAL are identical (in fact, ROSE doesn't even define x86_sal). The source_bits
argument contains the bits to be shifted into the result and is used only for SHRD and SHLD instructions.
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virtual |
Push floating-point value onto FP stack.
Pushes the specified value onto the floating-point circular stack. The current top-of-stack is the REG_ST register, but whose minor number is the value stored in the REG_ST_TOP register. The value in REG_ST_TOP (which must be concrete) is decremented modulo eight before being used.
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virtual |
Convert a signed value to a narrower unsigned type.
Returns the truncated source value except when the value cannot be represented in the narrower type, in which case the closest unsigned value is returned (zero or all bits set).
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virtual |
Convert a signed value to a narrower signed type.
Returns the truncated source value except when the value cannot be represented by the narrower type, in which case the closest signed value is returned. The closest signed value is either 0b1000...0 (minimum signed value) or 0b0111...1 (maximum signed value).
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virtual |
Convert an unsigned value to a narrower unsigned type.
Returns the truncated source value except when the value cannot be represented by the narrower type, in which case the closest unsigned value is returned.
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protected |
Definition at line 40 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anyAX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 51 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anyBX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 51 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anyCX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 51 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anyDX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 51 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RAX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 52 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RBX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 52 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RCX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 52 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RDX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 52 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_EAX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 53 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_EBX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 53 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_ECX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 53 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_EDX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 53 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_AX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 54 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_BX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 54 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_CX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 54 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_DX |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 54 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_AL |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 55 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_BL |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 55 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_CL |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 55 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_DL |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 55 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_AH |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 56 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_BH |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 56 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_CH |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 56 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_DH |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 56 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_R8 |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 58 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_R9 |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 58 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_R10 |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 58 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_R11 |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 58 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_R12 |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 59 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_R13 |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 59 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_R14 |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 59 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_R15 |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 59 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anyDI |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 61 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anySI |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 61 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anySP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 61 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anyBP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 61 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anyIP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 61 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RDI |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 62 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RSI |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 62 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RSP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 62 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RBP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 62 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RIP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 62 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_EDI |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 63 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_ESI |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 63 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_ESP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 63 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_EBP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 63 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_EIP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 63 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_DI |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 64 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_SI |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 64 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_SP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 64 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_BP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 64 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_IP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 64 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_CS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 66 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_DS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 66 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_ES |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 66 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_SS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 66 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_FS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 66 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_GS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 66 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_anyFLAGS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 68 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_RFLAGS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 68 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_EFLAGS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 68 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_FLAGS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 68 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_AF |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 69 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_CF |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 69 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_DF |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 69 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_OF |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 69 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_PF |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 69 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_SF |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 69 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_TF |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 69 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_ZF |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 69 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_ST0 |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 71 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_FPSTATUS |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 71 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_FPSTATUS_TOP |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 71 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_FPCTL |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 71 of file DispatcherX86.h.
RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics::DispatcherX86::REG_MXCSR |
Cached register.
This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the registerDictionary property is changed.
Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.
Definition at line 71 of file DispatcherX86.h.