DispatcherX86.h

#ifndef ROSE_BinaryAnalysis_InstructionSemantics2_DispatcherX86_H
#define ROSE_BinaryAnalysis_InstructionSemantics2_DispatcherX86_H
#include <featureTests.h>
#ifdef ROSE_ENABLE_BINARY_ANALYSIS

#include <Rose/BinaryAnalysis/InstructionSemantics2/BaseSemantics.h>
#include <Rose/BinaryAnalysis/Registers.h>

#include <boost/serialization/access.hpp>
#include <boost/serialization/base_object.hpp>
#include <boost/serialization/export.hpp>
#include <boost/serialization/split_member.hpp>

namespace Rose {
namespace BinaryAnalysis {
namespace InstructionSemantics2 {


//                                      Dispatcher

typedef boost::shared_ptr<class DispatcherX86> DispatcherX86Ptr;

class DispatcherX86: public BaseSemantics::Dispatcher {
public:
    using Super = BaseSemantics::Dispatcher;

    using Ptr = DispatcherX86Ptr;

protected:
    X86InstructionSize processorMode_;

public:
    RegisterDescriptor REG_anyAX, REG_anyBX, REG_anyCX, REG_anyDX;
    RegisterDescriptor REG_RAX,   REG_RBX,   REG_RCX,   REG_RDX;
    RegisterDescriptor REG_EAX,   REG_EBX,   REG_ECX,   REG_EDX;
    RegisterDescriptor REG_AX,    REG_BX,    REG_CX,    REG_DX;
    RegisterDescriptor REG_AL,    REG_BL,    REG_CL,    REG_DL;
    RegisterDescriptor REG_AH,    REG_BH,    REG_CH,    REG_DH;

    RegisterDescriptor REG_R8,    REG_R9,    REG_R10,   REG_R11;
    RegisterDescriptor REG_R12,   REG_R13,   REG_R14,   REG_R15;

    RegisterDescriptor REG_anyDI, REG_anySI, REG_anySP, REG_anyBP, REG_anyIP;
    RegisterDescriptor REG_RDI,   REG_RSI,   REG_RSP,   REG_RBP,   REG_RIP;
    RegisterDescriptor REG_EDI,   REG_ESI,   REG_ESP,   REG_EBP,   REG_EIP;
    RegisterDescriptor REG_DI,    REG_SI,    REG_SP,    REG_BP,    REG_IP;

    RegisterDescriptor REG_CS, REG_DS, REG_ES, REG_SS, REG_FS, REG_GS;

    RegisterDescriptor REG_anyFLAGS, REG_RFLAGS, REG_EFLAGS, REG_FLAGS;
    RegisterDescriptor REG_AF, REG_CF, REG_DF, REG_OF, REG_PF, REG_SF, REG_TF, REG_ZF;

    RegisterDescriptor REG_ST0, REG_FPSTATUS, REG_FPSTATUS_TOP, REG_FPCTL, REG_MXCSR;
#ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
private:
    friend class boost::serialization::access;

    template<class S>
    void save(S &s, const unsigned /*version*/) const {
        s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
        s & BOOST_SERIALIZATION_NVP(processorMode_);
    }
    
    template<class S>
    void load(S &s, const unsigned /*version*/) {
        s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
        s & BOOST_SERIALIZATION_NVP(processorMode_);
        regcache_init();
        iproc_init();
        memory_init();
    }

    BOOST_SERIALIZATION_SPLIT_MEMBER();
#endif
    
protected:
    // Prototypical constructor
    DispatcherX86()
        : BaseSemantics::Dispatcher(32, SgAsmX86Instruction::registersForInstructionSize(x86_insnsize_32)),
          processorMode_(x86_insnsize_32) {}

    // Prototypical constructor
    DispatcherX86(size_t addrWidth, const RegisterDictionary *regs/*=NULL*/)
        : BaseSemantics::Dispatcher(addrWidth, regs ? regs : SgAsmX86Instruction::registersForWidth(addrWidth)),
          processorMode_(SgAsmX86Instruction::instructionSizeForWidth(addrWidth)) {}

    // Normal constructor
    DispatcherX86(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
        : BaseSemantics::Dispatcher(ops, addrWidth, regs ? regs : SgAsmX86Instruction::registersForWidth(addrWidth)),
          processorMode_(SgAsmX86Instruction::instructionSizeForWidth(addrWidth)) {
        regcache_init();
        iproc_init();
        memory_init();
        initializeState(ops->currentState());
    }

public:
    void iproc_init();

    void regcache_init();

    void memory_init();

public:
    static DispatcherX86Ptr instance() {
        return DispatcherX86Ptr(new DispatcherX86);
    }

    static DispatcherX86Ptr instance(size_t addrWidth, const RegisterDictionary *regs=NULL) {
        return DispatcherX86Ptr(new DispatcherX86(addrWidth, regs));
    }

    static DispatcherX86Ptr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth,
                                     const RegisterDictionary *regs=NULL) {
        return DispatcherX86Ptr(new DispatcherX86(ops, addrWidth, regs));
    }

    virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0,
                                                const RegisterDictionary *regs=NULL) const override {
        if (0==addrWidth)
            addrWidth = addressWidth();
        if (NULL==regs)
            regs = registerDictionary();
        return instance(ops, addrWidth, regs);
    }

    static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &d) {
        DispatcherX86Ptr retval = boost::dynamic_pointer_cast<DispatcherX86>(d);
        assert(retval!=NULL);
        return retval;
    }

    X86InstructionSize processorMode() const { return processorMode_; }
    void processorMode(X86InstructionSize m) { processorMode_ = m; }
    virtual void set_register_dictionary(const RegisterDictionary *regdict) override;

    virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const;

    virtual RegisterDescriptor instructionPointerRegister() const override;
    virtual RegisterDescriptor stackPointerRegister() const override;
    virtual RegisterDescriptor stackFrameRegister() const override;
    virtual RegisterDescriptor callReturnRegister() const override;

    virtual int iprocKey(SgAsmInstruction *insn_) const override {
        SgAsmX86Instruction *insn = isSgAsmX86Instruction(insn_);
        assert(insn!=NULL);
        return insn->get_kind();
    }

    virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) override;

    virtual void initializeState(const BaseSemantics::StatePtr&) override;

    enum AccessMode { READ_REGISTER, PEEK_REGISTER };

    virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode = READ_REGISTER);

    virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result);

    virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result);

    virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result, const BaseSemantics::SValuePtr &cond);

    virtual BaseSemantics::SValuePtr parity(const BaseSemantics::SValuePtr &v);

    virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe);

    virtual BaseSemantics::SValuePtr greaterOrEqualToTen(const BaseSemantics::SValuePtr &value);

    virtual BaseSemantics::SValuePtr flagsCombo(X86InstructionKind k);

    virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix);

    virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag);

    virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b,
                                                    bool invertCarries, const BaseSemantics::SValuePtr &carryIn);
    virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b,
                                                    bool invertCarries, const BaseSemantics::SValuePtr &carryIn,
                                                    const BaseSemantics::SValuePtr &cond);
    virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry);

    virtual BaseSemantics::SValuePtr doRotateOperation(X86InstructionKind kind,
                                                       const BaseSemantics::SValuePtr &operand,
                                                       const BaseSemantics::SValuePtr &total_rotate,
                                                       size_t rotateSignificantBits);

    virtual BaseSemantics::SValuePtr doShiftOperation(X86InstructionKind kind,
                                                      const BaseSemantics::SValuePtr &operand,
                                                      const BaseSemantics::SValuePtr &source_bits,
                                                      const BaseSemantics::SValuePtr &total_shift,
                                                      size_t shiftSignificantBits);

    virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush);

    virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position);

    virtual void popFloatingPoint();

    virtual BaseSemantics::SValuePtr fixMemoryAddress(const BaseSemantics::SValuePtr &address) const;

    virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr&, size_t narrowerWidth);

    virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr&, size_t narrowerWidth);

    virtual BaseSemantics::SValuePtr saturateUnsignedToUnsigned(const BaseSemantics::SValuePtr&, size_t narrowerWidth);
};
        
//                                      Instruction processors

namespace X86 {

class InsnProcessor: public BaseSemantics::InsnProcessor {
public:
    typedef DispatcherX86 *D;
    typedef BaseSemantics::RiscOperators *Ops;
    typedef SgAsmX86Instruction *I;
    typedef const SgAsmExpressionPtrList &A;
    virtual void p(D, Ops, I, A) = 0;
    virtual void process(const BaseSemantics::DispatcherPtr&, SgAsmInstruction*) override;
    virtual void assert_args(I insn, A args, size_t nargs);
    void check_arg_width(D d, I insn, A args);
};

} // namespace

} // namespace
} // namespace
} // namespace

#ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
BOOST_CLASS_EXPORT_KEY(Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86);
#endif

#endif
#endif