ROSE  0.11.52.0
DispatcherX86.h
1 #ifndef ROSE_BinaryAnalysis_InstructionSemantics2_DispatcherX86_H
2 #define ROSE_BinaryAnalysis_InstructionSemantics2_DispatcherX86_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
5 
6 #include <Rose/BinaryAnalysis/InstructionSemantics2/BaseSemantics.h>
7 #include <Rose/BinaryAnalysis/Registers.h>
8 
9 #include <boost/serialization/access.hpp>
10 #include <boost/serialization/base_object.hpp>
11 #include <boost/serialization/export.hpp>
12 #include <boost/serialization/split_member.hpp>
13 
14 namespace Rose {
15 namespace BinaryAnalysis {
16 namespace InstructionSemantics2 {
17 
18 
20 // Dispatcher
22 
24 typedef boost::shared_ptr<class DispatcherX86> DispatcherX86Ptr;
25 
27 public:
30 
33 
34 protected:
35  X86InstructionSize processorMode_;
36 
37 public:
52 
55 
60 
62 
65 
69 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
70 private:
71  friend class boost::serialization::access;
72 
73  template<class S>
74  void save(S &s, const unsigned /*version*/) const {
75  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
76  s & BOOST_SERIALIZATION_NVP(processorMode_);
77  }
78 
79  template<class S>
80  void load(S &s, const unsigned /*version*/) {
81  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
82  s & BOOST_SERIALIZATION_NVP(processorMode_);
83  regcache_init();
84  iproc_init();
85  memory_init();
86  }
87 
88  BOOST_SERIALIZATION_SPLIT_MEMBER();
89 #endif
90 
91 protected:
92  // Prototypical constructor
93  DispatcherX86()
94  : BaseSemantics::Dispatcher(32, SgAsmX86Instruction::registersForInstructionSize(x86_insnsize_32)),
95  processorMode_(x86_insnsize_32) {}
96 
97  // Prototypical constructor
98  DispatcherX86(size_t addrWidth, const RegisterDictionary *regs/*=NULL*/)
99  : BaseSemantics::Dispatcher(addrWidth, regs ? regs : SgAsmX86Instruction::registersForWidth(addrWidth)),
100  processorMode_(SgAsmX86Instruction::instructionSizeForWidth(addrWidth)) {}
101 
102  // Normal constructor
103  DispatcherX86(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
104  : BaseSemantics::Dispatcher(ops, addrWidth, regs ? regs : SgAsmX86Instruction::registersForWidth(addrWidth)),
105  processorMode_(SgAsmX86Instruction::instructionSizeForWidth(addrWidth)) {
106  regcache_init();
107  iproc_init();
108  memory_init();
109  initializeState(ops->currentState());
110  }
111 
112 public:
114  void iproc_init();
115 
119  void regcache_init();
120 
122  void memory_init();
123 
124 public:
127  static DispatcherX86Ptr instance() {
128  return DispatcherX86Ptr(new DispatcherX86);
129  }
130 
133  static DispatcherX86Ptr instance(size_t addrWidth, const RegisterDictionary *regs=NULL) {
134  return DispatcherX86Ptr(new DispatcherX86(addrWidth, regs));
135  }
136 
138  static DispatcherX86Ptr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth,
139  const RegisterDictionary *regs=NULL) {
140  return DispatcherX86Ptr(new DispatcherX86(ops, addrWidth, regs));
141  }
142 
145  const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE {
146  if (0==addrWidth)
147  addrWidth = addressWidth();
148  if (NULL==regs)
149  regs = registerDictionary();
150  return instance(ops, addrWidth, regs);
151  }
152 
154  static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &d) {
155  DispatcherX86Ptr retval = boost::dynamic_pointer_cast<DispatcherX86>(d);
156  assert(retval!=NULL);
157  return retval;
158  }
159 
163  X86InstructionSize processorMode() const { return processorMode_; }
164  void processorMode(X86InstructionSize m) { processorMode_ = m; }
167  virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE;
168 
171  virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const;
172 
173  virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE;
174  virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE;
175  virtual RegisterDescriptor stackFrameRegister() const ROSE_OVERRIDE;
176  virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE;
177 
178  virtual int iprocKey(SgAsmInstruction *insn_) const ROSE_OVERRIDE {
179  SgAsmX86Instruction *insn = isSgAsmX86Instruction(insn_);
180  assert(insn!=NULL);
181  return insn->get_kind();
182  }
183 
184  virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) ROSE_OVERRIDE;
185 
186  virtual void initializeState(const BaseSemantics::StatePtr&) ROSE_OVERRIDE;
187 
188  enum AccessMode { READ_REGISTER, PEEK_REGISTER };
189 
193  virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode = READ_REGISTER);
194 
199  virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result);
200 
202  virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result);
203 
205  virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result, const BaseSemantics::SValuePtr &cond);
206 
209 
211  virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe);
212 
215 
218 
222 
230  virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag);
231 
236  bool invertCarries, const BaseSemantics::SValuePtr &carryIn);
238  bool invertCarries, const BaseSemantics::SValuePtr &carryIn,
239  const BaseSemantics::SValuePtr &cond);
244  virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry);
245 
250  const BaseSemantics::SValuePtr &operand,
251  const BaseSemantics::SValuePtr &total_rotate,
252  size_t rotateSignificantBits);
253 
260  const BaseSemantics::SValuePtr &operand,
261  const BaseSemantics::SValuePtr &source_bits,
262  const BaseSemantics::SValuePtr &total_shift,
263  size_t shiftSignificantBits);
264 
268  virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush);
269 
271  virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position);
272 
274  virtual void popFloatingPoint();
275 
278 
281  virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr&, size_t narrowerWidth);
282 
286  virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr&, size_t narrowerWidth);
287 
291 };
292 
294 // Instruction processors
296 
297 namespace X86 {
298 
306 public:
307  typedef DispatcherX86 *D;
309  typedef SgAsmX86Instruction *I;
310  typedef const SgAsmExpressionPtrList &A;
311  virtual void p(D, Ops, I, A) = 0;
312  virtual void process(const BaseSemantics::DispatcherPtr&, SgAsmInstruction*) ROSE_OVERRIDE;
313  virtual void assert_args(I insn, A args, size_t nargs);
314  void check_arg_width(D d, I insn, A args);
315 };
316 
317 } // namespace
318 
319 } // namespace
320 } // namespace
321 } // namespace
322 
323 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
325 #endif
326 
327 #endif
328 #endif
const RegisterDictionary * registerDictionary() const
Property: Register dictionary.
Definition: Dispatcher.h:195
void memory_init()
Make sure memory properties are set up correctly.
virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag)
Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction.
virtual void initializeState(const BaseSemantics::StatePtr &) ROSE_OVERRIDE
Initialize the state.
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) ROSE_OVERRIDE
Writes to an L-value expression.
virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const
Get list of common registers.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0, const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE
Virtual constructor.
virtual BaseSemantics::SValuePtr doRotateOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &total_rotate, size_t rotateSignificantBits)
Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes.
Base class for machine instructions.
virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE
Returns the instruction pointer register.
DispatcherX86Ptr Ptr
Shared-ownership pointer.
Definition: DispatcherX86.h:32
Base class for all x86 instruction processors.
static DispatcherX86Ptr instance(size_t addrWidth, const RegisterDictionary *regs=NULL)
Construct a prototyipcal dispatcher.
virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE
Returns the stack pointer register.
virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode=READ_REGISTER)
Architecture-specific read from register.
X86InstructionSize processorMode() const
CPU mode of operation.
virtual BaseSemantics::SValuePtr parity(const BaseSemantics::SValuePtr &v)
Returns true if byte v has an even number of bits set; false for an odd number.
void regcache_init()
Load the cached register descriptors.
RegisterDescriptor REG_FPSTATUS
Cached register.
Definition: DispatcherX86.h:66
Main namespace for the ROSE library.
virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result)
Set parity, sign, and zero flags appropriate for result value.
virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower unsigned type.
virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush)
Push floating-point value onto FP stack.
RegisterDescriptor REG_FPSTATUS_TOP
Cached register.
Definition: DispatcherX86.h:66
virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry)
Increments or decrements a value and adjusts flags.
RegisterDescriptor REG_anyFLAGS
Cached register.
Definition: DispatcherX86.h:63
virtual BaseSemantics::SValuePtr flagsCombo(X86InstructionKind k)
Return a Boolean for the specified flag combo for an instruction.
virtual int iprocKey(SgAsmInstruction *insn_) const ROSE_OVERRIDE
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn)
Adds two values and adjusts flags.
Base classes for instruction semantics.
Definition: Dispatcher.h:18
void iproc_init()
Loads the iproc table with instruction processing functors.
virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix)
Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction.
Describes (part of) a physical CPU register.
size_t addressWidth() const
Property: Width of memory addresses.
Definition: Dispatcher.h:225
virtual BaseSemantics::SValuePtr fixMemoryAddress(const BaseSemantics::SValuePtr &address) const
Extend or truncate value to propert memory address width.
virtual BaseSemantics::SValuePtr greaterOrEqualToTen(const BaseSemantics::SValuePtr &value)
Determines whether value is greater than or equal to ten.
virtual RegisterDescriptor stackFrameRegister() const ROSE_OVERRIDE
Returns the stack call frame register.
virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe)
Conditionally invert the bits of value.
Functor that knows how to dispatch a single kind of instruction.
Definition: Dispatcher.h:25
static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &d)
Dynamic cast to a DispatcherX86Ptr with assertion.
Instruction is for a 32-bit architecture.
Represents one Intel x86 machine instruction.
void processorMode(X86InstructionSize m)
CPU mode of operation.
boost::shared_ptr< class DispatcherX86 > DispatcherX86Ptr
Shared-ownership pointer to an x86 instruction dispatcher.
Definition: DispatcherX86.h:24
Base class for most instruction semantics RISC operators.
Definition: RiscOperators.h:48
const RegisterDictionary * regdict
See registerDictionary property.
Definition: Dispatcher.h:53
Base class for expressions.
Dispatches instructions through the RISC layer.
Definition: Dispatcher.h:44
virtual BaseSemantics::SValuePtr saturateUnsignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert an unsigned value to a narrower unsigned type.
virtual void popFloatingPoint()
Pop the top item from the floating point stack.
virtual BaseSemantics::SValuePtr doShiftOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &source_bits, const BaseSemantics::SValuePtr &total_shift, size_t shiftSignificantBits)
Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes...
static DispatcherX86Ptr instance()
Construct a prototypical dispatcher.
Rose::BinaryAnalysis::X86InstructionKind get_kind() const
Property: Instruction kind.
X86InstructionKind
List of all x86 instructions known to the ROSE disassembler/assembler.
virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower signed type.
Defines registers available for a particular architecture.
Definition: Registers.h:37
virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE
Returns the function call return address register.
virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position)
Read a value from the floating point stack.
X86InstructionSize
Intel x86 instruction size constants.
X86RepeatPrefix
Intel x86 instruction repeat prefix.
static DispatcherX86Ptr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result)
Architecture-specific write to register.