ROSE 0.11.145.250
DispatcherX86.h
1#ifndef ROSE_BinaryAnalysis_InstructionSemantics_DispatcherX86_H
2#define ROSE_BinaryAnalysis_InstructionSemantics_DispatcherX86_H
3#include <featureTests.h>
4#ifdef ROSE_ENABLE_BINARY_ANALYSIS
5#include <Rose/BinaryAnalysis/BasicTypes.h>
6
7#include <Rose/BinaryAnalysis/InstructionEnumsX86.h>
8#include <Rose/BinaryAnalysis/InstructionSemantics/BaseSemantics/Dispatcher.h>
9#include <Rose/BinaryAnalysis/RegisterDictionary.h>
10
11#include <sageContainer.h>
12
13#ifdef ROSE_ENABLE_BOOST_SERIALIZATION
14#include <boost/serialization/access.hpp>
15#include <boost/serialization/base_object.hpp>
16#include <boost/serialization/export.hpp>
17#include <boost/serialization/split_member.hpp>
18#endif
19
20namespace Rose {
21namespace BinaryAnalysis {
22namespace InstructionSemantics {
23
24
26// Dispatcher
28
30typedef boost::shared_ptr<class DispatcherX86> DispatcherX86Ptr;
31
34public:
37
40
41protected:
42 X86InstructionSize processorMode_;
43
44public:
59
62
67
69
72
76#ifdef ROSE_ENABLE_BOOST_SERIALIZATION
77private:
78 friend class boost::serialization::access;
79
80 template<class S>
81 void save(S &s, const unsigned /*version*/) const {
82 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
83 s & BOOST_SERIALIZATION_NVP(processorMode_);
84 }
85
86 template<class S>
87 void load(S &s, const unsigned /*version*/) {
88 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
89 s & BOOST_SERIALIZATION_NVP(processorMode_);
91 iproc_init();
93 }
94
95 BOOST_SERIALIZATION_SPLIT_MEMBER();
96#endif
97
98private:
99 DispatcherX86(); // used only by boost::serialization
100
101protected:
102 // Prototypical constructor
103 DispatcherX86(const Architecture::BaseConstPtr&);
104
105 // Normal constructor
107
108public:
109 ~DispatcherX86();
110
115
120
125
126public:
131
134
137
140
144 X86InstructionSize processorMode() const { return processorMode_; }
145 void processorMode(X86InstructionSize m) { processorMode_ = m; }
151
153 virtual RegisterDescriptor stackPointerRegister() const override;
154 virtual RegisterDescriptor stackFrameRegister() const override;
155 virtual int iprocKey(SgAsmInstruction *insn_) const override;
156 virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) override;
157 virtual void initializeState(const BaseSemantics::StatePtr&) override;
158
159 enum AccessMode { READ_REGISTER, PEEK_REGISTER };
160
164 virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode = READ_REGISTER);
165
171
173 virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result);
174
177
180
183
186
189
192 virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix);
193
201 virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, Address insn_va, bool honorZeroFlag);
202
207 bool invertCarries, const BaseSemantics::SValuePtr &carryIn);
209 bool invertCarries, const BaseSemantics::SValuePtr &carryIn,
210 const BaseSemantics::SValuePtr &cond);
215 virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry);
216
221 const BaseSemantics::SValuePtr &operand,
222 const BaseSemantics::SValuePtr &total_rotate,
223 size_t rotateSignificantBits);
224
231 const BaseSemantics::SValuePtr &operand,
232 const BaseSemantics::SValuePtr &source_bits,
233 const BaseSemantics::SValuePtr &total_shift,
234 size_t shiftSignificantBits);
235
239 virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush);
240
243
245 virtual void popFloatingPoint();
246
249
253
258
262};
263
265// Instruction processors
267
268namespace X86 {
269
277public:
278 typedef DispatcherX86 *D;
280 typedef SgAsmX86Instruction *I;
281 typedef const SgAsmExpressionPtrList &A;
282 virtual void p(D, Ops, I, A) = 0;
283 virtual void process(const BaseSemantics::DispatcherPtr&, SgAsmInstruction*) override;
284 virtual void assert_args(I insn, A args, size_t nargs);
285 void check_arg_width(D d, I insn, A args);
286};
287
288} // namespace
289
290} // namespace
291} // namespace
292} // namespace
293
294#ifdef ROSE_ENABLE_BOOST_SERIALIZATION
296#endif
297
298#endif
299#endif
Dispatches instructions through the RISC layer.
Definition Dispatcher.h:46
Functor that knows how to dispatch a single kind of instruction.
Definition Dispatcher.h:27
Base class for most instruction semantics RISC operators.
Semantically evaluates Intel x86 instructions.
virtual void popFloatingPoint()
Pop the top item from the floating point stack.
static DispatcherX86Ptr instance(const Architecture::BaseConstPtr &, const BaseSemantics::RiscOperatorsPtr &)
Constructor.
void memory_init()
Make sure memory properties are set up correctly.
virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position)
Read a value from the floating point stack.
virtual BaseSemantics::SValuePtr fixMemoryAddress(const BaseSemantics::SValuePtr &address) const
Extend or truncate value to propert memory address width.
virtual BaseSemantics::SValuePtr doRotateOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &total_rotate, size_t rotateSignificantBits)
Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes.
static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &)
Dynamic cast to a DispatcherX86Ptr with assertion.
RegisterDescriptor REG_FPSTATUS_TOP
Cached register.
void processorMode(X86InstructionSize m)
CPU mode of operation.
virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe)
Conditionally invert the bits of value.
virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn)
Adds two values and adjusts flags.
virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode=READ_REGISTER)
Architecture-specific read from register.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &) const override
Virtual constructor.
virtual BaseSemantics::SValuePtr flagsCombo(X86InstructionKind k)
Return a Boolean for the specified flag combo for an instruction.
virtual int iprocKey(SgAsmInstruction *insn_) const override
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table.
virtual RegisterDescriptor stackFrameRegister() const override
Returns the stack call frame register.
virtual BaseSemantics::SValuePtr saturateUnsignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert an unsigned value to a narrower unsigned type.
virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry)
Increments or decrements a value and adjusts flags.
virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result)
Architecture-specific write to register.
virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn, const BaseSemantics::SValuePtr &cond)
Adds two values and adjusts flags.
virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result)
Set parity, sign, and zero flags appropriate for result value.
X86InstructionSize processorMode() const
CPU mode of operation.
virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower unsigned type.
virtual BaseSemantics::SValuePtr parity(const BaseSemantics::SValuePtr &v)
Returns true if byte v has an even number of bits set; false for an odd number.
void iproc_init()
Loads the iproc table with instruction processing functors.
DispatcherX86Ptr Ptr
Shared-ownership pointer.
virtual void initializeState(const BaseSemantics::StatePtr &) override
Initialize the state.
static DispatcherX86Ptr instance(const Architecture::BaseConstPtr &)
Construct a prototypical dispatcher.
void regcache_init()
Load the cached register descriptors.
virtual BaseSemantics::SValuePtr doShiftOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &source_bits, const BaseSemantics::SValuePtr &total_shift, size_t shiftSignificantBits)
Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes.
virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix)
Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction.
virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const
Get list of common registers.
virtual RegisterDescriptor stackPointerRegister() const override
Returns the stack pointer register.
virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) override
Writes to an L-value expression.
virtual BaseSemantics::SValuePtr greaterOrEqualToTen(const BaseSemantics::SValuePtr &value)
Determines whether value is greater than or equal to ten.
virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, Address insn_va, bool honorZeroFlag)
Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction.
virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result, const BaseSemantics::SValuePtr &cond)
Conditionally set parity, sign, and zero flags appropriate for result value.
virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush)
Push floating-point value onto FP stack.
virtual RegisterDescriptor instructionPointerRegister() const override
Returns the instruction pointer register.
virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower signed type.
Base class for all x86 instruction processors.
Describes (part of) a physical CPU register.
Rose::BinaryAnalysis::RegisterDescriptors RegisterDescriptors
List of register descriptors in dictionary.
Base class for expressions.
Base class for machine instructions.
Represents one Intel x86 machine instruction.
std::shared_ptr< const Base > BaseConstPtr
Reference counted pointer for Architecture::Base.
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
boost::shared_ptr< class DispatcherX86 > DispatcherX86Ptr
Shared-ownership pointer to an x86 instruction dispatcher.
X86InstructionKind
List of all x86 instructions known to the ROSE disassembler/assembler.
std::uint64_t Address
Address.
Definition Address.h:11
The ROSE library.