ROSE  0.11.22.0
DispatcherX86.h
1 #ifndef ROSE_DispatcherX86_H
2 #define ROSE_DispatcherX86_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
5 
6 #include <BaseSemantics2.h>
7 #include <Registers.h>
8 
9 #include <boost/serialization/access.hpp>
10 #include <boost/serialization/base_object.hpp>
11 #include <boost/serialization/export.hpp>
12 #include <boost/serialization/split_member.hpp>
13 
14 namespace Rose {
15 namespace BinaryAnalysis {
16 namespace InstructionSemantics2 {
17 
18 
20 // Dispatcher
22 
24 typedef boost::shared_ptr<class DispatcherX86> DispatcherX86Ptr;
25 
27 public:
29 
30 protected:
31  X86InstructionSize processorMode_;
32 
33 public:
48 
51 
56 
58 
61 
65 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
66 private:
67  friend class boost::serialization::access;
68 
69  template<class S>
70  void save(S &s, const unsigned /*version*/) const {
71  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
72  s & BOOST_SERIALIZATION_NVP(processorMode_);
73  }
74 
75  template<class S>
76  void load(S &s, const unsigned /*version*/) {
77  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
78  s & BOOST_SERIALIZATION_NVP(processorMode_);
79  regcache_init();
80  iproc_init();
81  memory_init();
82  }
83 
84  BOOST_SERIALIZATION_SPLIT_MEMBER();
85 #endif
86 
87 protected:
88  // Prototypical constructor
89  DispatcherX86()
90  : BaseSemantics::Dispatcher(32, SgAsmX86Instruction::registersForInstructionSize(x86_insnsize_32)),
91  processorMode_(x86_insnsize_32) {}
92 
93  // Prototypical constructor
94  DispatcherX86(size_t addrWidth, const RegisterDictionary *regs/*=NULL*/)
95  : BaseSemantics::Dispatcher(addrWidth, regs ? regs : SgAsmX86Instruction::registersForWidth(addrWidth)),
96  processorMode_(SgAsmX86Instruction::instructionSizeForWidth(addrWidth)) {}
97 
98  // Normal constructor
99  DispatcherX86(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
100  : BaseSemantics::Dispatcher(ops, addrWidth, regs ? regs : SgAsmX86Instruction::registersForWidth(addrWidth)),
101  processorMode_(SgAsmX86Instruction::instructionSizeForWidth(addrWidth)) {
102  regcache_init();
103  iproc_init();
104  memory_init();
105  initializeState(ops->currentState());
106  }
107 
108 public:
110  void iproc_init();
111 
113  void regcache_init();
114 
116  void memory_init();
117 
118 public:
121  static DispatcherX86Ptr instance() {
122  return DispatcherX86Ptr(new DispatcherX86);
123  }
124 
127  static DispatcherX86Ptr instance(size_t addrWidth, const RegisterDictionary *regs=NULL) {
128  return DispatcherX86Ptr(new DispatcherX86(addrWidth, regs));
129  }
130 
132  static DispatcherX86Ptr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth,
133  const RegisterDictionary *regs=NULL) {
134  return DispatcherX86Ptr(new DispatcherX86(ops, addrWidth, regs));
135  }
136 
139  const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE {
140  if (0==addrWidth)
141  addrWidth = addressWidth();
142  if (NULL==regs)
143  regs = get_register_dictionary();
144  return instance(ops, addrWidth, regs);
145  }
146 
148  static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &d) {
149  DispatcherX86Ptr retval = boost::dynamic_pointer_cast<DispatcherX86>(d);
150  assert(retval!=NULL);
151  return retval;
152  }
153 
157  X86InstructionSize processorMode() const { return processorMode_; }
158  void processorMode(X86InstructionSize m) { processorMode_ = m; }
161  virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE;
162 
165  virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const;
166 
167  virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE;
168  virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE;
169  virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE;
170 
171  virtual int iproc_key(SgAsmInstruction *insn_) const ROSE_OVERRIDE {
172  SgAsmX86Instruction *insn = isSgAsmX86Instruction(insn_);
173  assert(insn!=NULL);
174  return insn->get_kind();
175  }
176 
177  virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) ROSE_OVERRIDE;
178 
179  virtual void initializeState(const BaseSemantics::StatePtr&) ROSE_OVERRIDE;
180 
181  enum AccessMode { READ_REGISTER, PEEK_REGISTER };
182 
186  virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode = READ_REGISTER);
187 
192  virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result);
193 
195  virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result);
196 
198  virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result, const BaseSemantics::SValuePtr &cond);
199 
202 
204  virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe);
205 
208 
211 
215 
223  virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag);
224 
229  bool invertCarries, const BaseSemantics::SValuePtr &carryIn);
231  bool invertCarries, const BaseSemantics::SValuePtr &carryIn,
232  const BaseSemantics::SValuePtr &cond);
237  virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry);
238 
243  const BaseSemantics::SValuePtr &operand,
244  const BaseSemantics::SValuePtr &total_rotate,
245  size_t rotateSignificantBits);
246 
253  const BaseSemantics::SValuePtr &operand,
254  const BaseSemantics::SValuePtr &source_bits,
255  const BaseSemantics::SValuePtr &total_shift,
256  size_t shiftSignificantBits);
257 
261  virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush);
262 
264  virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position);
265 
267  virtual void popFloatingPoint();
268 
271 
274  virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr&, size_t narrowerWidth);
275 
279  virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr&, size_t narrowerWidth);
280 
284 };
285 
287 // Instruction processors
289 
290 namespace X86 {
291 
299 public:
300  typedef DispatcherX86 *D;
302  typedef SgAsmX86Instruction *I;
303  typedef const SgAsmExpressionPtrList &A;
304  virtual void p(D, Ops, I, A) = 0;
305  virtual void process(const BaseSemantics::DispatcherPtr&, SgAsmInstruction*) ROSE_OVERRIDE;
306  virtual void assert_args(I insn, A args, size_t nargs);
307  void check_arg_width(D d, I insn, A args);
308 };
309 
310 } // namespace
311 
312 } // namespace
313 } // namespace
314 } // namespace
315 
316 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
318 #endif
319 
320 #endif
321 #endif
void memory_init()
Make sure memory properties are set up correctly.
virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag)
Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction.
virtual void initializeState(const BaseSemantics::StatePtr &) ROSE_OVERRIDE
Initialize the state.
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) ROSE_OVERRIDE
Writes to an L-value expression.
virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const
Get list of common registers.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0, const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE
Virtual constructor.
virtual BaseSemantics::SValuePtr doRotateOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &total_rotate, size_t rotateSignificantBits)
Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes.
Base class for machine instructions.
virtual int iproc_key(SgAsmInstruction *insn_) const ROSE_OVERRIDE
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE
Returns the instruction pointer register.
Base class for all x86 instruction processors.
static DispatcherX86Ptr instance(size_t addrWidth, const RegisterDictionary *regs=NULL)
Construct a prototyipcal dispatcher.
virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE
Returns the stack pointer register.
virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode=READ_REGISTER)
Architecture-specific read from register.
X86InstructionSize processorMode() const
CPU mode of operation.
virtual BaseSemantics::SValuePtr parity(const BaseSemantics::SValuePtr &v)
Returns true if byte v has an even number of bits set; false for an odd number.
void regcache_init()
Load the cached register descriptors.
RegisterDescriptor REG_FPSTATUS
Cached register.
Definition: DispatcherX86.h:62
Main namespace for the ROSE library.
virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result)
Set parity, sign, and zero flags appropriate for result value.
virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower unsigned type.
virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush)
Push floating-point value onto FP stack.
virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE
Access the register dictionary.
virtual const RegisterDictionary * get_register_dictionary() const
Access the register dictionary.
RegisterDescriptor REG_FPSTATUS_TOP
Cached register.
Definition: DispatcherX86.h:62
virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry)
Increments or decrements a value and adjusts flags.
RegisterDescriptor REG_anyFLAGS
Cached register.
Definition: DispatcherX86.h:59
virtual BaseSemantics::SValuePtr flagsCombo(X86InstructionKind k)
Return a Boolean for the specified flag combo for an instruction.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn)
Adds two values and adjusts flags.
void iproc_init()
Loads the iproc table with instruction processing functors.
virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix)
Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction.
Describes (part of) a physical CPU register.
size_t addressWidth() const
Property: Width of memory addresses.
virtual BaseSemantics::SValuePtr fixMemoryAddress(const BaseSemantics::SValuePtr &address) const
Extend or truncate value to propert memory address width.
virtual BaseSemantics::SValuePtr greaterOrEqualToTen(const BaseSemantics::SValuePtr &value)
Determines whether value is greater than or equal to ten.
virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe)
Conditionally invert the bits of value.
Functor that knows how to dispatch a single kind of instruction.
static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &d)
Dynamic cast to a DispatcherX86Ptr with assertion.
Instruction is for a 32-bit architecture.
Represents one Intel x86 machine instruction.
void processorMode(X86InstructionSize m)
CPU mode of operation.
boost::shared_ptr< class DispatcherX86 > DispatcherX86Ptr
Shared-ownership pointer to an x86 instruction dispatcher.
Definition: DispatcherX86.h:24
Base class for most instruction semantics RISC operators.
const RegisterDictionary * regdict
See set_register_dictionary().
Base class for expressions.
virtual BaseSemantics::SValuePtr saturateUnsignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert an unsigned value to a narrower unsigned type.
virtual void popFloatingPoint()
Pop the top item from the floating point stack.
virtual BaseSemantics::SValuePtr doShiftOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &source_bits, const BaseSemantics::SValuePtr &total_shift, size_t shiftSignificantBits)
Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes...
static DispatcherX86Ptr instance()
Construct a prototypical dispatcher.
Rose::BinaryAnalysis::X86InstructionKind get_kind() const
Property: Instruction kind.
X86InstructionKind
List of all x86 instructions known to the ROSE disassembler/assembler.
virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower signed type.
Defines registers available for a particular architecture.
Definition: Registers.h:38
virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE
Returns the function call return address register.
virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position)
Read a value from the floating point stack.
X86InstructionSize
Intel x86 instruction size constants.
X86RepeatPrefix
Intel x86 instruction repeat prefix.
static DispatcherX86Ptr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result)
Architecture-specific write to register.