ROSE  0.9.9.109
DispatcherX86.h
1 #ifndef ROSE_DispatcherX86_H
2 #define ROSE_DispatcherX86_H
3 
4 #include "BaseSemantics2.h"
5 
6 #include <boost/serialization/access.hpp>
7 #include <boost/serialization/base_object.hpp>
8 #include <boost/serialization/export.hpp>
9 #include <boost/serialization/split_member.hpp>
10 
11 namespace Rose {
12 namespace BinaryAnalysis {
13 namespace InstructionSemantics2 {
14 
15 
17 // Dispatcher
19 
21 typedef boost::shared_ptr<class DispatcherX86> DispatcherX86Ptr;
22 
24 public:
26 
27 protected:
28  X86InstructionSize processorMode_;
29 
30 public:
45 
48 
53 
55 
58 
62 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
63 private:
64  friend class boost::serialization::access;
65 
66  template<class S>
67  void save(S &s, const unsigned version) const {
68  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
69  s & BOOST_SERIALIZATION_NVP(processorMode_);
70  }
71 
72  template<class S>
73  void load(S &s, const unsigned version) {
74  s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
75  s & BOOST_SERIALIZATION_NVP(processorMode_);
76  regcache_init();
77  iproc_init();
78  memory_init();
79  }
80 
81  BOOST_SERIALIZATION_SPLIT_MEMBER();
82 #endif
83 
84 protected:
85  // Prototypical constructor
86  DispatcherX86()
87  : BaseSemantics::Dispatcher(32, SgAsmX86Instruction::registersForInstructionSize(x86_insnsize_32)),
88  processorMode_(x86_insnsize_32) {}
89 
90  // Prototypical constructor
91  DispatcherX86(size_t addrWidth, const RegisterDictionary *regs/*=NULL*/)
92  : BaseSemantics::Dispatcher(addrWidth, regs ? regs : SgAsmX86Instruction::registersForWidth(addrWidth)),
93  processorMode_(SgAsmX86Instruction::instructionSizeForWidth(addrWidth)) {}
94 
95  // Normal constructor
96  DispatcherX86(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
97  : BaseSemantics::Dispatcher(ops, addrWidth, regs ? regs : SgAsmX86Instruction::registersForWidth(addrWidth)),
98  processorMode_(SgAsmX86Instruction::instructionSizeForWidth(addrWidth)) {
99  regcache_init();
100  iproc_init();
101  memory_init();
102  }
103 
104 public:
106  void iproc_init();
107 
109  void regcache_init();
110 
112  void memory_init();
113 
114 public:
117  static DispatcherX86Ptr instance() {
118  return DispatcherX86Ptr(new DispatcherX86);
119  }
120 
123  static DispatcherX86Ptr instance(size_t addrWidth, const RegisterDictionary *regs=NULL) {
124  return DispatcherX86Ptr(new DispatcherX86(addrWidth, regs));
125  }
126 
128  static DispatcherX86Ptr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth,
129  const RegisterDictionary *regs=NULL) {
130  return DispatcherX86Ptr(new DispatcherX86(ops, addrWidth, regs));
131  }
132 
135  const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE {
136  if (0==addrWidth)
137  addrWidth = addressWidth();
138  if (NULL==regs)
139  regs = get_register_dictionary();
140  return instance(ops, addrWidth, regs);
141  }
142 
144  static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &d) {
145  DispatcherX86Ptr retval = boost::dynamic_pointer_cast<DispatcherX86>(d);
146  assert(retval!=NULL);
147  return retval;
148  }
149 
153  X86InstructionSize processorMode() const { return processorMode_; }
154  void processorMode(X86InstructionSize m) { processorMode_ = m; }
157  virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE;
158 
161  virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const;
162 
163  virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE;
164 
165  virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE;
166 
167  virtual int iproc_key(SgAsmInstruction *insn_) const ROSE_OVERRIDE {
168  SgAsmX86Instruction *insn = isSgAsmX86Instruction(insn_);
169  assert(insn!=NULL);
170  return insn->get_kind();
171  }
172 
173  virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) ROSE_OVERRIDE;
174 
175  enum AccessMode { READ_REGISTER, PEEK_REGISTER };
176 
180  virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode = READ_REGISTER);
181 
186  virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result);
187 
189  virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result);
190 
192  virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result, const BaseSemantics::SValuePtr &cond);
193 
196 
198  virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe);
199 
202 
204  virtual BaseSemantics::SValuePtr flagsCombo(X86InstructionKind k);
205 
208  virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix);
209 
217  virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag);
218 
223  bool invertCarries, const BaseSemantics::SValuePtr &carryIn);
225  bool invertCarries, const BaseSemantics::SValuePtr &carryIn,
226  const BaseSemantics::SValuePtr &cond);
231  virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry);
232 
236  virtual BaseSemantics::SValuePtr doRotateOperation(X86InstructionKind kind,
237  const BaseSemantics::SValuePtr &operand,
238  const BaseSemantics::SValuePtr &total_rotate,
239  size_t rotateSignificantBits);
240 
246  virtual BaseSemantics::SValuePtr doShiftOperation(X86InstructionKind kind,
247  const BaseSemantics::SValuePtr &operand,
248  const BaseSemantics::SValuePtr &source_bits,
249  const BaseSemantics::SValuePtr &total_shift,
250  size_t shiftSignificantBits);
251 
255  virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush);
256 
258  virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position);
259 
261  virtual void popFloatingPoint();
262 
265 
268  virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr&, size_t narrowerWidth);
269 
273  virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr&, size_t narrowerWidth);
274 
278 };
279 
281 // Instruction processors
283 
284 namespace X86 {
285 
293 public:
294  typedef DispatcherX86 *D;
296  typedef SgAsmX86Instruction *I;
297  typedef const SgAsmExpressionPtrList &A;
298  virtual void p(D, Ops, I, A) = 0;
299  virtual void process(const BaseSemantics::DispatcherPtr&, SgAsmInstruction*) ROSE_OVERRIDE;
300  virtual void assert_args(I insn, A args, size_t nargs);
301  void check_arg_width(D d, I insn, A args);
302 };
303 
304 } // namespace
305 
306 } // namespace
307 } // namespace
308 } // namespace
309 
310 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
312 #endif
313 
314 #endif
void memory_init()
Make sure memory is set up correctly.
virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag)
Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction.
virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) ROSE_OVERRIDE
Writes to an L-value expression.
virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const
Get list of common registers.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0, const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE
Virtual constructor.
virtual BaseSemantics::SValuePtr doRotateOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &total_rotate, size_t rotateSignificantBits)
Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes.
Base class for machine instructions.
X86InstructionKind get_kind() const
Property: Instruction kind.
virtual int iproc_key(SgAsmInstruction *insn_) const ROSE_OVERRIDE
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE
Returns the instruction pointer register.
Base class for all x86 instruction processors.
static DispatcherX86Ptr instance(size_t addrWidth, const RegisterDictionary *regs=NULL)
Construct a prototyipcal dispatcher.
virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE
Returns the stack pointer register.
virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode=READ_REGISTER)
Architecture-specific read from register.
X86InstructionSize processorMode() const
CPU mode of operation.
virtual BaseSemantics::SValuePtr parity(const BaseSemantics::SValuePtr &v)
Returns true if byte v has an even number of bits set; false for an odd number.
void regcache_init()
Load the cached register descriptors.
RegisterDescriptor REG_FPSTATUS
Cached register.
Definition: DispatcherX86.h:59
Main namespace for the ROSE library.
Describes (part of) a physical CPU register.
virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result)
Set parity, sign, and zero flags appropriate for result value.
virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower unsigned type.
virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush)
Push floating-point value onto FP stack.
virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE
Access the register dictionary.
virtual const RegisterDictionary * get_register_dictionary() const
Access the register dictionary.
RegisterDescriptor REG_FPSTATUS_TOP
Cached register.
Definition: DispatcherX86.h:59
virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry)
Increments or decrements a value and adjusts flags.
RegisterDescriptor REG_anyFLAGS
Cached register.
Definition: DispatcherX86.h:56
virtual BaseSemantics::SValuePtr flagsCombo(X86InstructionKind k)
Return a Boolean for the specified flag combo for an instruction.
virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn)
Adds two values and adjusts flags.
boost::shared_ptr< class Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
Base classes for instruction semantics.
void iproc_init()
Loads the iproc table with instruction processing functors.
virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix)
Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction.
size_t addressWidth() const
Property: Width of memory addresses.
boost::shared_ptr< class RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
virtual BaseSemantics::SValuePtr fixMemoryAddress(const BaseSemantics::SValuePtr &address) const
Extend or truncate value to propert memory address width.
virtual BaseSemantics::SValuePtr greaterOrEqualToTen(const BaseSemantics::SValuePtr &value)
Determines whether value is greater than or equal to ten.
virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe)
Conditionally invert the bits of value.
Functor that knows how to dispatch a single kind of instruction.
static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &d)
Dynamic cast to a DispatcherX86Ptr with assertion.
Represents one Intel x86 machine instruction.
void processorMode(X86InstructionSize m)
CPU mode of operation.
Defines registers available for a particular architecture.
Definition: Registers.h:32
boost::shared_ptr< class DispatcherX86 > DispatcherX86Ptr
Shared-ownership pointer to an x86 instruction dispatcher.
Definition: DispatcherX86.h:21
Base class for most instruction semantics RISC operators.
const RegisterDictionary * regdict
See set_register_dictionary().
Base class for expressions.
virtual BaseSemantics::SValuePtr saturateUnsignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert an unsigned value to a narrower unsigned type.
virtual void popFloatingPoint()
Pop the top item from the floating point stack.
virtual BaseSemantics::SValuePtr doShiftOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &source_bits, const BaseSemantics::SValuePtr &total_shift, size_t shiftSignificantBits)
Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes...
static DispatcherX86Ptr instance()
Construct a prototypical dispatcher.
virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower signed type.
virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position)
Read a value from the floating point stack.
static DispatcherX86Ptr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result)
Architecture-specific write to register.