ROSE 0.11.145.147
DispatcherX86.h
1#ifndef ROSE_BinaryAnalysis_InstructionSemantics_DispatcherX86_H
2#define ROSE_BinaryAnalysis_InstructionSemantics_DispatcherX86_H
3#include <featureTests.h>
4#ifdef ROSE_ENABLE_BINARY_ANALYSIS
5#include <Rose/BinaryAnalysis/BasicTypes.h>
6
7#include <Rose/BinaryAnalysis/InstructionEnumsX86.h>
8#include <Rose/BinaryAnalysis/InstructionSemantics/BaseSemantics/Dispatcher.h>
9#include <Rose/BinaryAnalysis/RegisterDictionary.h>
10
11#include <sageContainer.h>
12
13#include <boost/serialization/access.hpp>
14#include <boost/serialization/base_object.hpp>
15#include <boost/serialization/export.hpp>
16#include <boost/serialization/split_member.hpp>
17
18namespace Rose {
19namespace BinaryAnalysis {
20namespace InstructionSemantics {
21
22
24// Dispatcher
26
28typedef boost::shared_ptr<class DispatcherX86> DispatcherX86Ptr;
29
32public:
35
38
39protected:
40 X86InstructionSize processorMode_;
41
42public:
57
60
65
67
70
74#ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
75private:
76 friend class boost::serialization::access;
77
78 template<class S>
79 void save(S &s, const unsigned /*version*/) const {
80 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
81 s & BOOST_SERIALIZATION_NVP(processorMode_);
82 }
83
84 template<class S>
85 void load(S &s, const unsigned /*version*/) {
86 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
87 s & BOOST_SERIALIZATION_NVP(processorMode_);
89 iproc_init();
91 }
92
93 BOOST_SERIALIZATION_SPLIT_MEMBER();
94#endif
95
96private:
97 DispatcherX86(); // used only by boost::serialization
98
99protected:
100 // Prototypical constructor
101 DispatcherX86(const Architecture::BaseConstPtr&);
102
103 // Normal constructor
105
106public:
107 ~DispatcherX86();
108
113
118
123
124public:
129
132
135
138
142 X86InstructionSize processorMode() const { return processorMode_; }
143 void processorMode(X86InstructionSize m) { processorMode_ = m; }
149
151 virtual RegisterDescriptor stackPointerRegister() const override;
152 virtual RegisterDescriptor stackFrameRegister() const override;
153 virtual RegisterDescriptor callReturnRegister() const override;
154 virtual int iprocKey(SgAsmInstruction *insn_) const override;
155 virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) override;
156 virtual void initializeState(const BaseSemantics::StatePtr&) override;
157
158 enum AccessMode { READ_REGISTER, PEEK_REGISTER };
159
163 virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode = READ_REGISTER);
164
170
172 virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result);
173
176
179
182
185
188
191 virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix);
192
200 virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag);
201
206 bool invertCarries, const BaseSemantics::SValuePtr &carryIn);
208 bool invertCarries, const BaseSemantics::SValuePtr &carryIn,
209 const BaseSemantics::SValuePtr &cond);
214 virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry);
215
220 const BaseSemantics::SValuePtr &operand,
221 const BaseSemantics::SValuePtr &total_rotate,
222 size_t rotateSignificantBits);
223
230 const BaseSemantics::SValuePtr &operand,
231 const BaseSemantics::SValuePtr &source_bits,
232 const BaseSemantics::SValuePtr &total_shift,
233 size_t shiftSignificantBits);
234
238 virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush);
239
242
244 virtual void popFloatingPoint();
245
248
252
257
261};
262
264// Instruction processors
266
267namespace X86 {
268
276public:
277 typedef DispatcherX86 *D;
279 typedef SgAsmX86Instruction *I;
280 typedef const SgAsmExpressionPtrList &A;
281 virtual void p(D, Ops, I, A) = 0;
282 virtual void process(const BaseSemantics::DispatcherPtr&, SgAsmInstruction*) override;
283 virtual void assert_args(I insn, A args, size_t nargs);
284 void check_arg_width(D d, I insn, A args);
285};
286
287} // namespace
288
289} // namespace
290} // namespace
291} // namespace
292
293#ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
295#endif
296
297#endif
298#endif
Dispatches instructions through the RISC layer.
Definition Dispatcher.h:43
Functor that knows how to dispatch a single kind of instruction.
Definition Dispatcher.h:24
Base class for most instruction semantics RISC operators.
Semantically evaluates Intel x86 instructions.
virtual void popFloatingPoint()
Pop the top item from the floating point stack.
static DispatcherX86Ptr instance(const Architecture::BaseConstPtr &, const BaseSemantics::RiscOperatorsPtr &)
Constructor.
void memory_init()
Make sure memory properties are set up correctly.
virtual RegisterDescriptor callReturnRegister() const override
Returns the function call return address register.
virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position)
Read a value from the floating point stack.
virtual BaseSemantics::SValuePtr fixMemoryAddress(const BaseSemantics::SValuePtr &address) const
Extend or truncate value to propert memory address width.
virtual BaseSemantics::SValuePtr doRotateOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &total_rotate, size_t rotateSignificantBits)
Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes.
static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &)
Dynamic cast to a DispatcherX86Ptr with assertion.
RegisterDescriptor REG_FPSTATUS_TOP
Cached register.
void processorMode(X86InstructionSize m)
CPU mode of operation.
virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe)
Conditionally invert the bits of value.
virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn)
Adds two values and adjusts flags.
virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag)
Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction.
virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode=READ_REGISTER)
Architecture-specific read from register.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &) const override
Virtual constructor.
virtual BaseSemantics::SValuePtr flagsCombo(X86InstructionKind k)
Return a Boolean for the specified flag combo for an instruction.
virtual int iprocKey(SgAsmInstruction *insn_) const override
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table.
virtual RegisterDescriptor stackFrameRegister() const override
Returns the stack call frame register.
virtual BaseSemantics::SValuePtr saturateUnsignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert an unsigned value to a narrower unsigned type.
virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry)
Increments or decrements a value and adjusts flags.
virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result)
Architecture-specific write to register.
virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn, const BaseSemantics::SValuePtr &cond)
Adds two values and adjusts flags.
virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result)
Set parity, sign, and zero flags appropriate for result value.
X86InstructionSize processorMode() const
CPU mode of operation.
virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower unsigned type.
virtual BaseSemantics::SValuePtr parity(const BaseSemantics::SValuePtr &v)
Returns true if byte v has an even number of bits set; false for an odd number.
void iproc_init()
Loads the iproc table with instruction processing functors.
DispatcherX86Ptr Ptr
Shared-ownership pointer.
virtual void initializeState(const BaseSemantics::StatePtr &) override
Initialize the state.
static DispatcherX86Ptr instance(const Architecture::BaseConstPtr &)
Construct a prototypical dispatcher.
void regcache_init()
Load the cached register descriptors.
virtual BaseSemantics::SValuePtr doShiftOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &source_bits, const BaseSemantics::SValuePtr &total_shift, size_t shiftSignificantBits)
Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes.
virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix)
Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction.
virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const
Get list of common registers.
virtual RegisterDescriptor stackPointerRegister() const override
Returns the stack pointer register.
virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) override
Writes to an L-value expression.
virtual BaseSemantics::SValuePtr greaterOrEqualToTen(const BaseSemantics::SValuePtr &value)
Determines whether value is greater than or equal to ten.
virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result, const BaseSemantics::SValuePtr &cond)
Conditionally set parity, sign, and zero flags appropriate for result value.
virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush)
Push floating-point value onto FP stack.
virtual RegisterDescriptor instructionPointerRegister() const override
Returns the instruction pointer register.
virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower signed type.
Base class for all x86 instruction processors.
Describes (part of) a physical CPU register.
Rose::BinaryAnalysis::RegisterDescriptors RegisterDescriptors
List of register descriptors in dictionary.
Base class for expressions.
Base class for machine instructions.
Represents one Intel x86 machine instruction.
std::shared_ptr< const Base > BaseConstPtr
Reference counted pointer for Architecture::Base.
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
boost::shared_ptr< class DispatcherX86 > DispatcherX86Ptr
Shared-ownership pointer to an x86 instruction dispatcher.
X86InstructionKind
List of all x86 instructions known to the ROSE disassembler/assembler.
The ROSE library.