1 #ifndef ROSE_DispatcherX86_H
2 #define ROSE_DispatcherX86_H
3 #include <featureTests.h>
4 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
6 #include <BaseSemantics2.h>
9 #include <boost/serialization/access.hpp>
10 #include <boost/serialization/base_object.hpp>
11 #include <boost/serialization/export.hpp>
12 #include <boost/serialization/split_member.hpp>
16 namespace InstructionSemantics2 {
65 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
67 friend class boost::serialization::access;
70 void save(S &s,
const unsigned )
const {
71 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
72 s & BOOST_SERIALIZATION_NVP(processorMode_);
76 void load(S &s,
const unsigned ) {
77 s & BOOST_SERIALIZATION_BASE_OBJECT_NVP(Super);
78 s & BOOST_SERIALIZATION_NVP(processorMode_);
84 BOOST_SERIALIZATION_SPLIT_MEMBER();
94 DispatcherX86(
size_t addrWidth,
const RegisterDictionary *regs)
144 return instance(ops, addrWidth, regs);
149 DispatcherX86Ptr retval = boost::dynamic_pointer_cast<
DispatcherX86>(d);
150 assert(retval!=NULL);
181 enum AccessMode { READ_REGISTER, PEEK_REGISTER };
245 size_t rotateSignificantBits);
256 size_t shiftSignificantBits);
303 typedef const SgAsmExpressionPtrList &A;
304 virtual void p(D, Ops, I, A) = 0;
306 virtual void assert_args(I insn, A args,
size_t nargs);
307 void check_arg_width(D d, I insn, A args);
316 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
void memory_init()
Make sure memory properties are set up correctly.
virtual void repLeave(X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag)
Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction.
virtual void initializeState(const BaseSemantics::StatePtr &) ROSE_OVERRIDE
Initialize the state.
boost::shared_ptr< RiscOperators > RiscOperatorsPtr
Shared-ownership pointer to a RISC operators object.
RegisterDescriptor REG_FS
Cached register.
virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) ROSE_OVERRIDE
Writes to an L-value expression.
RegisterDescriptor REG_DF
Cached register.
RegisterDescriptor REG_SS
Cached register.
virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const
Get list of common registers.
RegisterDescriptor REG_SF
Cached register.
virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0, const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE
Virtual constructor.
virtual BaseSemantics::SValuePtr doRotateOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &total_rotate, size_t rotateSignificantBits)
Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes.
RegisterDescriptor REG_anyCX
Cached register.
RegisterDescriptor REG_OF
Cached register.
RegisterDescriptor REG_AH
Cached register.
RegisterDescriptor REG_R10
Cached register.
RegisterDescriptor REG_EAX
Cached register.
RegisterDescriptor REG_EIP
Cached register.
Base class for machine instructions.
RegisterDescriptor REG_AL
Cached register.
virtual int iproc_key(SgAsmInstruction *insn_) const ROSE_OVERRIDE
Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table...
virtual RegisterDescriptor instructionPointerRegister() const ROSE_OVERRIDE
Returns the instruction pointer register.
RegisterDescriptor REG_RSI
Cached register.
RegisterDescriptor REG_PF
Cached register.
Base class for all x86 instruction processors.
static DispatcherX86Ptr instance(size_t addrWidth, const RegisterDictionary *regs=NULL)
Construct a prototyipcal dispatcher.
virtual RegisterDescriptor stackPointerRegister() const ROSE_OVERRIDE
Returns the stack pointer register.
RegisterDescriptor REG_RDI
Cached register.
virtual BaseSemantics::SValuePtr readRegister(RegisterDescriptor, AccessMode mode=READ_REGISTER)
Architecture-specific read from register.
X86InstructionSize processorMode() const
CPU mode of operation.
RegisterDescriptor REG_SP
Cached register.
virtual BaseSemantics::SValuePtr parity(const BaseSemantics::SValuePtr &v)
Returns true if byte v has an even number of bits set; false for an odd number.
RegisterDescriptor REG_anySP
Cached register.
void regcache_init()
Load the cached register descriptors.
RegisterDescriptor REG_FPSTATUS
Cached register.
RegisterDescriptor REG_ESP
Cached register.
RegisterDescriptor REG_R9
Cached register.
Main namespace for the ROSE library.
RegisterDescriptor REG_RFLAGS
Cached register.
RegisterDescriptor REG_ECX
Cached register.
RegisterDescriptor REG_RAX
Cached register.
virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result)
Set parity, sign, and zero flags appropriate for result value.
virtual BaseSemantics::SValuePtr saturateSignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower unsigned type.
RegisterDescriptor REG_ESI
Cached register.
RegisterDescriptor REG_DI
Cached register.
virtual void pushFloatingPoint(const BaseSemantics::SValuePtr &valueToPush)
Push floating-point value onto FP stack.
virtual void set_register_dictionary(const RegisterDictionary *regdict) ROSE_OVERRIDE
Access the register dictionary.
RegisterDescriptor REG_BH
Cached register.
virtual const RegisterDictionary * get_register_dictionary() const
Access the register dictionary.
RegisterDescriptor REG_TF
Cached register.
RegisterDescriptor REG_FPSTATUS_TOP
Cached register.
virtual BaseSemantics::SValuePtr doIncOperation(const BaseSemantics::SValuePtr &a, bool dec, bool setCarry)
Increments or decrements a value and adjusts flags.
RegisterDescriptor REG_anyFLAGS
Cached register.
RegisterDescriptor REG_BX
Cached register.
RegisterDescriptor REG_R13
Cached register.
virtual BaseSemantics::SValuePtr flagsCombo(X86InstructionKind k)
Return a Boolean for the specified flag combo for an instruction.
RegisterDescriptor REG_EDX
Cached register.
boost::shared_ptr< Dispatcher > DispatcherPtr
Shared-ownership pointer to a semantics instruction dispatcher.
RegisterDescriptor REG_RCX
Cached register.
RegisterDescriptor REG_R11
Cached register.
virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn)
Adds two values and adjusts flags.
RegisterDescriptor REG_CS
Cached register.
RegisterDescriptor REG_anySI
Cached register.
RegisterDescriptor REG_RIP
Cached register.
Base classes for instruction semantics.
RegisterDescriptor REG_SI
Cached register.
void iproc_init()
Loads the iproc table with instruction processing functors.
RegisterDescriptor REG_R12
Cached register.
virtual BaseSemantics::SValuePtr repEnter(X86RepeatPrefix)
Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction.
RegisterDescriptor REG_CL
Cached register.
Describes (part of) a physical CPU register.
size_t addressWidth() const
Property: Width of memory addresses.
RegisterDescriptor REG_CF
Cached register.
virtual BaseSemantics::SValuePtr fixMemoryAddress(const BaseSemantics::SValuePtr &address) const
Extend or truncate value to propert memory address width.
virtual BaseSemantics::SValuePtr greaterOrEqualToTen(const BaseSemantics::SValuePtr &value)
Determines whether value is greater than or equal to ten.
RegisterDescriptor REG_EBX
Cached register.
RegisterDescriptor REG_R8
Cached register.
RegisterDescriptor REG_ES
Cached register.
virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe)
Conditionally invert the bits of value.
RegisterDescriptor REG_ST0
Cached register.
Functor that knows how to dispatch a single kind of instruction.
RegisterDescriptor REG_anyDI
Cached register.
static DispatcherX86Ptr promote(const BaseSemantics::DispatcherPtr &d)
Dynamic cast to a DispatcherX86Ptr with assertion.
Instruction is for a 32-bit architecture.
Represents one Intel x86 machine instruction.
RegisterDescriptor REG_AF
Cached register.
void processorMode(X86InstructionSize m)
CPU mode of operation.
RegisterDescriptor REG_BP
Cached register.
boost::shared_ptr< class DispatcherX86 > DispatcherX86Ptr
Shared-ownership pointer to an x86 instruction dispatcher.
Base class for most instruction semantics RISC operators.
RegisterDescriptor REG_DH
Cached register.
const RegisterDictionary * regdict
See set_register_dictionary().
Base class for expressions.
Dispatches instructions through the RISC layer.
RegisterDescriptor REG_CH
Cached register.
RegisterDescriptor REG_anyBP
Cached register.
RegisterDescriptor REG_anyAX
Cached register.
RegisterDescriptor REG_RSP
Cached register.
virtual BaseSemantics::SValuePtr saturateUnsignedToUnsigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert an unsigned value to a narrower unsigned type.
virtual void popFloatingPoint()
Pop the top item from the floating point stack.
RegisterDescriptor REG_FLAGS
Cached register.
RegisterDescriptor REG_DX
Cached register.
RegisterDescriptor REG_RDX
Cached register.
RegisterDescriptor REG_EFLAGS
Cached register.
RegisterDescriptor REG_MXCSR
Cached register.
RegisterDescriptor REG_EBP
Cached register.
virtual BaseSemantics::SValuePtr doShiftOperation(X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &source_bits, const BaseSemantics::SValuePtr &total_shift, size_t shiftSignificantBits)
Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes...
RegisterDescriptor REG_ZF
Cached register.
static DispatcherX86Ptr instance()
Construct a prototypical dispatcher.
Rose::BinaryAnalysis::X86InstructionKind get_kind() const
Property: Instruction kind.
RegisterDescriptor REG_anyIP
Cached register.
RegisterDescriptor REG_RBX
Cached register.
RegisterDescriptor REG_DL
Cached register.
X86InstructionKind
List of all x86 instructions known to the ROSE disassembler/assembler.
virtual BaseSemantics::SValuePtr saturateSignedToSigned(const BaseSemantics::SValuePtr &, size_t narrowerWidth)
Convert a signed value to a narrower signed type.
Defines registers available for a particular architecture.
virtual RegisterDescriptor callReturnRegister() const ROSE_OVERRIDE
Returns the function call return address register.
virtual BaseSemantics::SValuePtr readFloatingPointStack(size_t position)
Read a value from the floating point stack.
RegisterDescriptor REG_R14
Cached register.
RegisterDescriptor REG_IP
Cached register.
RegisterDescriptor REG_anyBX
Cached register.
RegisterDescriptor REG_CX
Cached register.
RegisterDescriptor REG_FPCTL
Cached register.
X86InstructionSize
Intel x86 instruction size constants.
RegisterDescriptor REG_BL
Cached register.
RegisterDescriptor REG_RBP
Cached register.
RegisterDescriptor REG_R15
Cached register.
RegisterDescriptor REG_AX
Cached register.
RegisterDescriptor REG_anyDX
Cached register.
RegisterDescriptor REG_DS
Cached register.
X86RepeatPrefix
Intel x86 instruction repeat prefix.
RegisterDescriptor REG_EDI
Cached register.
RegisterDescriptor REG_GS
Cached register.
static DispatcherX86Ptr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs=NULL)
Constructor.
virtual void writeRegister(RegisterDescriptor, const BaseSemantics::SValuePtr &result)
Architecture-specific write to register.