2 #ifndef ROSE_BinaryAnalysis_DisassemblerCil_H
3 #define ROSE_BinaryAnalysis_DisassemblerCil_H
4 #include <featureTests.h>
5 #ifdef ROSE_ENABLE_BINARY_ANALYSIS
6 #include <Rose/BinaryAnalysis/Disassembler/Base.h>
8 #include <Rose/BinaryAnalysis/InstructionEnumsCil.h>
9 #include "BitPattern.h"
11 #include <boost/serialization/access.hpp>
12 #include <boost/serialization/base_object.hpp>
13 #include <boost/serialization/export.hpp>
14 #include <boost/serialization/split_member.hpp>
17 namespace BinaryAnalysis {
26 struct State: boost::noncopyable {
34 : insn_va(0), niwords(0), niwords_used(0) {}
49 : name(name), family(family), pattern(pattern) {}
66 typedef std::list<Cil*> IdisList;
67 typedef std::vector<IdisList> IdisTable;
70 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
72 friend class boost::serialization::access;
75 void serialize_common(S &s,
const unsigned ) {
77 s & BOOST_SERIALIZATION_NVP(family);
82 void save(S &s,
const unsigned version)
const {
83 serialize_common(s, version);
87 void load(S &s,
const unsigned version) {
88 serialize_common(s, version);
92 BOOST_SERIALIZATION_SPLIT_MEMBER();
109 explicit DisassemblerCil(
CilFamily family)
122 AddressSet *successors=NULL)
override;
128 virtual Unparser::BasePtr
unparser()
const override;
130 typedef std::pair<SgAsmExpression*, SgAsmExpression*> ExpressionPair;
135 Cil *
find_idis(uint16_t *insn_bytes,
size_t nbytes)
const;
176 size_t bit_offset=0)
const;
264 #ifdef ROSE_HAVE_BOOST_SERIALIZATION_LIB
SgAsmRegisterReferenceExpression * makeStatusRegister(State &) const
Create a reference to the status register.
SgAsmRegisterReferenceExpression * makeConditionCodeRegister(State &) const
Create a reference to the condition code register.
SgAsmRegisterReferenceExpression * makeColdFireControlRegister(State &, unsigned regnum) const
Create control register for ColdFire cpu.
Base class for references to a machine register.
CilFamily
Members of the Motorola Coldfire family of m68k processors.
SgAsmType * makeType(State &, CilDataFormat) const
Create a ROSE data type for Cil data format.
Base class for machine instructions.
CilMacRegister
CIL MAC registers.
SgAsmRegisterReferenceExpression * makeRegister(RegisterDescriptor) const
Generic ways to make a register.
SgAsmIntegerValueExpression * makeImmediateValue(State &, CilDataFormat fmt, unsigned value) const
Create an integer expression from a specified value.
MemoryMap::Ptr map
Map from which to read instruction words.
CilInstructionKind
CIL instruction types.
virtual bool canDisassemble(SgAsmGenericHeader *) const override
Predicate determining the suitability of a disassembler for a specific file header.
Main namespace for the ROSE library.
SgAsmMemoryReferenceExpression * makeAddressRegisterPostIncrement(State &, unsigned regnum, CilDataFormat fmt) const
Make a memory reference expression using an address register in post-increment mode.
size_t niwords_used
High water number of instruction words used by instructionWord().
SgAsmRegisterNames * makeFPRegistersFromMask(State &, unsigned mask, CilDataFormat fmt, bool reverse=false) const
Create a list of floating-point data registers.
Reference-counting intrusive smart pointer.
SgAsmRegisterReferenceExpression * makeProgramCounter(State &) const
Create a reference to the program counter register.
SgAsmCilInstruction * makeInstruction(rose_addr_t start_va, CilInstructionKind, const std::string &mnemonic, SgAsmExpression *arg0=NULL, SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL, SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL, SgAsmExpression *arg5=NULL, SgAsmExpression *arg6=NULL, SgAsmExpression *arg7=NULL) const
Build an instruction.
virtual SgAsmInstruction * makeUnknownInstruction(const Disassembler::Exception &) override
Makes an unknown instruction from an exception.
SgAsmRegisterNames * makeRegistersFromMask(State &, unsigned mask, CilDataFormat fmt, bool reverse=false) const
Create a list of data and/or address registers.
MemoryMapPtr Ptr
Reference counting pointer.
Reference to memory locations.
Cil * find_idis(uint16_t *insn_bytes, size_t nbytes) const
Find an instruction-specific disassembler.
An ordered list of registers.
Sawyer::SharedPointer< DisassemblerCil > Ptr
Reference counting pointer.
CilDataFormat
M68k data formats for floating-point operations.
Base class for integer values.
CilFamily get_family() const
Returns ISA family specified in constructor.
uint16_t iwords[11]
Instruction words.
Describes (part of) a physical CPU register.
SgAsmRegisterReferenceExpression * makeMacAccumulatorRegister(State &, unsigned accumIndex) const
Create a MAC accumulator register.
SgAsmRegisterReferenceExpression * makeFPRegister(State &, unsigned regnum) const
Create a floating point register.
SgAsmExpression * makeEffectiveAddress(State &, unsigned modreg, CilDataFormat fmt, size_t ext_offset) const
Create an expression for Cil "x" or "y".
SgAsmRegisterReferenceExpression * makeDataRegister(State &, unsigned regnum, CilDataFormat, size_t bit_offset=0) const
Create a data register reference expression.
size_t extensionWordsUsed(State &) const
Returns number of instruction words referenced so far in the current instruction. ...
size_t niwords
Number of instruction words read.
void start_instruction(State &state, const MemoryMap::Ptr &map, rose_addr_t start_va) const
Called by disassembleOne() to initialize the disassembler state for the next instruction.
ExpressionPair makeOffsetWidthPair(State &, unsigned extension_word) const
Create an offset width pair from an extension word.
Base class for expressions.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &, rose_addr_t start_va, AddressSet *successors=NULL) override
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
All CIL Instruction sets.
virtual Unparser::BasePtr unparser() const override
Unparser.
SgAsmRegisterReferenceExpression * makeDataAddressRegister(State &, unsigned regnum, CilDataFormat fmt, size_t bit_offset=0) const
Create either a data or address register reference expression.
Disassembler for CIL instruction set architectures.
static Ptr instance()
Allocating constructor.
uint16_t instructionWord(State &, size_t n) const
Return the Nth instruction word.
rose_addr_t insn_va
Address of instruction.
Base class for binary types.
SgAsmRegisterReferenceExpression * makeMacRegister(State &, CilMacRegister) const
Create a MAC register reference expression.
Interface for disassembling a single instruction.
SgAsmRegisterReferenceExpression * makeAddressRegister(State &, unsigned regnum, CilDataFormat, size_t bit_offset=0) const
Create an address register reference expression.
SgAsmExpression * makeAddress(State &, SgAsmExpression *expr) const
Converts a memory-reference expression to an address.
virtual Disassembler::BasePtr clone() const override
Creates a new copy of a disassembler.
SgAsmIntegerValueExpression * makeImmediateExtension(State &, CilDataFormat fmt, size_t ext_word_idx) const
Create an integer expression from extension words.
void insert_idis(Cil *)
Insert an instruction-specific disassembler.
Sawyer::SharedPointer< Base > BasePtr
Reference counted pointer for disassemblers.
Virtual base class for instruction disassemblers.
SgAsmMemoryReferenceExpression * makeAddressRegisterPreDecrement(State &, unsigned regnum, CilDataFormat fmt) const
Make a memory reference expression using an address register in pre-decrement mode.