ROSE  0.9.10.75
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Rose::BinaryAnalysis::DisassemblerMips Class Reference

Description

Definition at line 12 of file DisassemblerMips.h.

Inheritance diagram for Rose::BinaryAnalysis::DisassemblerMips:
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Collaboration diagram for Rose::BinaryAnalysis::DisassemblerMips:
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Classes

class  Mips32
 Interface for disassembling a single instruction. More...
 

Public Member Functions

 DisassemblerMips (ByteOrder::Endianness sex=ByteOrder::ORDER_MSB)
 Create a MIPS disassembler. More...
 
virtual DisassemblerMipsclone () const ROSE_OVERRIDE
 Creates a new copy of a disassembler. More...
 
virtual bool canDisassemble (SgAsmGenericHeader *) const ROSE_OVERRIDE
 Predicate determining the suitability of a disassembler for a specific file header. More...
 
virtual SgAsmInstructiondisassembleOne (const MemoryMap::Ptr &, rose_addr_t start_va, AddressSet *successors=NULL) ROSE_OVERRIDE
 This is the lowest level disassembly function and is implemented in the architecture-specific subclasses. More...
 
virtual SgAsmInstructionmakeUnknownInstruction (const Disassembler::Exception &) ROSE_OVERRIDE
 Makes an unknown instruction from an exception. More...
 
virtual Unparser::BasePtr unparser () const ROSE_OVERRIDE
 Unparser. More...
 
Mips32find_idis (unsigned insn_bits)
 Find an instruction-specific disassembler. More...
 
void insert_idis (Mips32 *, bool replace=false)
 Insert an instruction-specific disassembler. More...
 
SgAsmMipsInstructiondisassemble_insn (unsigned insn_bits)
 Disassemble a single instruction. More...
 
rose_addr_t get_ip () const
 Obtain the virtual address for the instruction being disassembled. More...
 
SgAsmMipsInstructionmakeInstruction (MipsInstructionKind, const std::string &mnemonic, SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL, SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL)
 Create a new instruction. More...
 
SgAsmRegisterReferenceExpressionmakeRegister (unsigned regnum)
 Create a new general purpose register reference expression. More...
 
SgAsmRegisterReferenceExpressionmakeFpRegister (unsigned regnum)
 Create a new floating point register reference expression. More...
 
SgAsmRegisterReferenceExpressionmakeCp0Register (unsigned regnum, unsigned sel)
 Create a new register reference for Coprocessor 0. More...
 
SgAsmRegisterReferenceExpressionmakeCp2Register (unsigned regnum)
 Create a new register reference for Coprocessor 2. More...
 
SgAsmRegisterReferenceExpressionmakeFpccRegister (unsigned cc)
 Create a new floating point condition flag register reference expression. More...
 
SgAsmRegisterReferenceExpressionmakeCp2ccRegister (unsigned cc)
 Create a new register reference for a COP2 condition code. More...
 
SgAsmRegisterReferenceExpressionmakeHwRegister (unsigned regnum)
 Create a new register reference for a hardware register. More...
 
SgAsmRegisterReferenceExpressionmakeShadowRegister (unsigned regnum)
 Create a new register reference for a shadow GPR. More...
 
SgAsmIntegerValueExpressionmakeImmediate8 (unsigned value, size_t bit_offset, size_t nbits)
 Create a new 8-bit value expression from an 8-bit value. More...
 
SgAsmIntegerValueExpressionmakeImmediate16 (unsigned value, size_t bit_offset, size_t nbits)
 Create a new 16-bit value expression from a 16-bit value. More...
 
SgAsmIntegerValueExpressionmakeImmediate32 (unsigned value, size_t bit_offset, size_t nbits)
 Create a new 32-bit value expression from a 32-bit value. More...
 
SgAsmIntegerValueExpressionmakeBranchTargetRelative (unsigned offset16, size_t bit_offset, size_t nbits)
 Create a 32-bit PC-relative branch target address from a 16-bit offset. More...
 
SgAsmIntegerValueExpressionmakeBranchTargetAbsolute (unsigned insn_index, size_t bit_offset, size_t nbits)
 Create a 32-bit branch address from an instruction index value. More...
 
SgAsmBinaryAddmakeRegisterOffset (unsigned gprnum, unsigned offset16)
 Build an expression for an offset from a register. More...
 
SgAsmBinaryAddmakeRegisterIndexed (unsigned base_gprnum, unsigned index_gprnum)
 Build a register index expression. More...
 
SgAsmMemoryReferenceExpressionmakeMemoryReference (SgAsmExpression *addr, SgAsmType *type)
 Build a memory reference expression. More...
 
- Public Member Functions inherited from Rose::BinaryAnalysis::Disassembler
virtual RegisterDescriptor instructionPointerRegister () const
 Returns the register that points to instructions. More...
 
virtual RegisterDescriptor stackPointerRegister () const
 Returns the register that points to the stack. More...
 
virtual RegisterDescriptor stackSegmentRegister () const
 Returns the segment register for accessing the stack. More...
 
const Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::DispatcherPtrdispatcher () const
 Return an instruction semantics dispatcher if possible. More...
 
SgAsmInstructiondisassembleOne (const unsigned char *buf, rose_addr_t buf_va, size_t buf_size, rose_addr_t start_va, AddressSet *successors=NULL)
 Similar in functionality to the disassembleOne method that takes a MemoryMap argument, except the content buffer is mapped 1:1 to virtual memory beginning at the specified address. More...
 
void mark_referenced_instructions (SgAsmInterpretation *, const MemoryMap::Ptr &, const InstructionMap &)
 Marks parts of the file that correspond to instructions as having been referenced. More...
 
AddressSet get_block_successors (const InstructionMap &, bool *complete)
 Calculates the successor addresses of a basic block and adds them to a successors set. More...
 
const std::string & name () const
 Property: Name by which disassembler is registered.
 
void name (const std::string &s)
 Property: Name by which disassembler is registered.
 
ByteOrder::Endianness byteOrder () const
 Property: Byte order of instructions in memory.
 
void byteOrder (ByteOrder::Endianness sex)
 Property: Byte order of instructions in memory.
 
size_t wordSizeBytes () const
 Property: Basic word size in bytes.
 
void wordSizeBytes (size_t nbytes)
 Property: Basic word size in bytes.
 
void registerDictionary (const RegisterDictionary *rdict)
 Properties: Register dictionary. More...
 
const RegisterDictionaryregisterDictionary () const
 Properties: Register dictionary. More...
 
const CallingConvention::DictionarycallingConventions () const
 Property: Calling convention dictionary. More...
 
CallingConvention::DictionarycallingConventions ()
 Properties: Register dictionary. More...
 
void callingConventions (const CallingConvention::Dictionary &d)
 Properties: Register dictionary. More...
 

Protected Member Functions

void init (ByteOrder::Endianness)
 

Protected Attributes

std::vector< Mips32 * > idis_table
 Table of instruction-specific disassemblers. More...
 
rose_addr_t insn_va
 Address of instruction currently being disassembled. More...
 
- Protected Attributes inherited from Rose::BinaryAnalysis::Disassembler
const RegisterDictionaryp_registers
 Description of registers available for this platform. More...
 
RegisterDescriptor REG_IP
 
RegisterDescriptor REG_SP
 
RegisterDescriptor REG_SS
 Register descriptors initialized during construction. More...
 
ByteOrder::Endianness p_byteOrder
 Byte order of instructions in memory. More...
 
size_t p_wordSizeBytes
 Basic word size in bytes. More...
 
std::string p_name
 Name by which this dissassembler is registered. More...
 
InstructionSemantics2::BaseSemantics::DispatcherPtr p_proto_dispatcher
 Prototypical dispatcher for creating real dispatchers.
 

Additional Inherited Members

- Public Types inherited from Rose::BinaryAnalysis::Disassembler
typedef std::set< rose_addr_t > AddressSet
 An AddressSet contains virtual addresses (alternatively, relative virtual addresses) for such things as specifying which virtual addresses should be disassembled. More...
 
typedef Map< rose_addr_t, SgAsmInstruction * > InstructionMap
 The InstructionMap is a mapping from (absolute) virtual address to disassembled instruction. More...
 
- Static Public Member Functions inherited from Rose::BinaryAnalysis::Disassembler
static void registerSubclass (Disassembler *)
 Register a disassembler instance. More...
 
static Disassemblerlookup (SgAsmGenericHeader *)
 Finds a suitable disassembler. More...
 
static std::vector< std::string > isaNames ()
 List of names recognized by lookup. More...
 
static Disassemblerlookup (SgAsmInterpretation *)
 Finds a suitable disassembler. More...
 
static Disassemblerlookup (const std::string &)
 Finds a suitable disassembler. More...
 
static void initDiagnostics ()
 Initializes and registers disassembler diagnostic streams. More...
 
- Static Public Attributes inherited from Rose::BinaryAnalysis::Disassembler
static Sawyer::Message::Facility mlog
 Disassembler diagnostic streams. More...
 
- Static Protected Attributes inherited from Rose::BinaryAnalysis::Disassembler
static std::vector< Disassembler * > disassemblers
 List of disassembler subclasses. More...
 

Constructor & Destructor Documentation

Rose::BinaryAnalysis::DisassemblerMips::DisassemblerMips ( ByteOrder::Endianness  sex = ByteOrder::ORDER_MSB)
inlineexplicit

Create a MIPS disassembler.

MIPS executables can be big- or little-endian.

Definition at line 17 of file DisassemblerMips.h.

Referenced by clone().

Member Function Documentation

virtual DisassemblerMips* Rose::BinaryAnalysis::DisassemblerMips::clone ( ) const
inlinevirtual

Creates a new copy of a disassembler.

The new copy has all the same settings as the original.

Thread safety: The thread safety of this virtual method depends on the implementation in the subclass.

Implements Rose::BinaryAnalysis::Disassembler.

Definition at line 19 of file DisassemblerMips.h.

References DisassemblerMips().

virtual bool Rose::BinaryAnalysis::DisassemblerMips::canDisassemble ( SgAsmGenericHeader ) const
virtual

Predicate determining the suitability of a disassembler for a specific file header.

If this disassembler is capable of disassembling machine code described by the specified file header, then this predicate returns true, otherwise it returns false.

Thread safety: The thread safety of this virtual method depends on the implementation in the subclass.

Implements Rose::BinaryAnalysis::Disassembler.

virtual SgAsmInstruction* Rose::BinaryAnalysis::DisassemblerMips::disassembleOne ( const MemoryMap::Ptr map,
rose_addr_t  start_va,
AddressSet successors = NULL 
)
virtual

This is the lowest level disassembly function and is implemented in the architecture-specific subclasses.

It disassembles one instruction at the specified virtual address. The map is a mapping from virtual addresses to buffer and enables instructions to span file segments that are mapped contiguously in virtual memory by the loader but which might not be contiguous in the file. The instruction's successor virtual addresses are added to the optional successor set (note that successors of an individual instruction can also be obtained via SgAsmInstruction::getSuccessors). If the instruction cannot be disassembled then an exception is thrown and the successors set is not modified.

Thread safety: The safety of this method depends on its implementation in the subclass. In any case, no other thread can be modifying the MemoryMap or successors set at the same time.

Implements Rose::BinaryAnalysis::Disassembler.

virtual SgAsmInstruction* Rose::BinaryAnalysis::DisassemblerMips::makeUnknownInstruction ( const Disassembler::Exception )
virtual

Makes an unknown instruction from an exception.

Thread safety: The safety of this method depends on its implementation in the subclass.

Implements Rose::BinaryAnalysis::Disassembler.

virtual Unparser::BasePtr Rose::BinaryAnalysis::DisassemblerMips::unparser ( ) const
virtual

Unparser.

Returns an unparser suitable for unparsing the same instruction set architecture as recognized and produced by this disassembler.

Implements Rose::BinaryAnalysis::Disassembler.

Mips32* Rose::BinaryAnalysis::DisassemblerMips::find_idis ( unsigned  insn_bits)

Find an instruction-specific disassembler.

Using the specified instruction bits, search for and return an instruction-specific disassembler. Returns null if no appropriate disassembler can be found. Instruction-specific disassemblers know how to disassemble specific instruction types (or groups of closely related instructions).

void Rose::BinaryAnalysis::DisassemblerMips::insert_idis ( Mips32 ,
bool  replace = false 
)

Insert an instruction-specific disassembler.

If replace is false (the default) then the table must not already contain an entry that has the same mask and match values. The pointers are managed by the caller and must not be deleted while they are in the table.

SgAsmMipsInstruction* Rose::BinaryAnalysis::DisassemblerMips::disassemble_insn ( unsigned  insn_bits)

Disassemble a single instruction.

Given the bits of a MIPS32 instruction, attempt to disassemble the instruction. If the bits can be disassembled, then a new SgAsmMipsInstruction is returned, otherwise it returns the null pointer. It may also throw an exception if a valid instruction-specific disassembler can be found but the instruction is malformed.

rose_addr_t Rose::BinaryAnalysis::DisassemblerMips::get_ip ( ) const
inline

Obtain the virtual address for the instruction being disassembled.

Definition at line 65 of file DisassemblerMips.h.

References insn_va.

SgAsmMipsInstruction* Rose::BinaryAnalysis::DisassemblerMips::makeInstruction ( MipsInstructionKind  ,
const std::string &  mnemonic,
SgAsmExpression arg1 = NULL,
SgAsmExpression arg2 = NULL,
SgAsmExpression arg3 = NULL,
SgAsmExpression arg4 = NULL 
)

Create a new instruction.

SgAsmRegisterReferenceExpression* Rose::BinaryAnalysis::DisassemblerMips::makeRegister ( unsigned  regnum)

Create a new general purpose register reference expression.

SgAsmRegisterReferenceExpression* Rose::BinaryAnalysis::DisassemblerMips::makeFpRegister ( unsigned  regnum)

Create a new floating point register reference expression.

SgAsmRegisterReferenceExpression* Rose::BinaryAnalysis::DisassemblerMips::makeCp0Register ( unsigned  regnum,
unsigned  sel 
)

Create a new register reference for Coprocessor 0.

SgAsmRegisterReferenceExpression* Rose::BinaryAnalysis::DisassemblerMips::makeCp2Register ( unsigned  regnum)

Create a new register reference for Coprocessor 2.

SgAsmRegisterReferenceExpression* Rose::BinaryAnalysis::DisassemblerMips::makeFpccRegister ( unsigned  cc)

Create a new floating point condition flag register reference expression.

The return value is a reference to one of the bits from the FCSR register. If cc is zero then bit 23 is referenced, otherwise bit 24+cc is referenced. The cc value must be zero through seven, inclusive.

SgAsmRegisterReferenceExpression* Rose::BinaryAnalysis::DisassemblerMips::makeCp2ccRegister ( unsigned  cc)

Create a new register reference for a COP2 condition code.

See COP2ConditionCode() in the MIPS reference manual.

SgAsmRegisterReferenceExpression* Rose::BinaryAnalysis::DisassemblerMips::makeHwRegister ( unsigned  regnum)

Create a new register reference for a hardware register.

See the RDHWR instruction documentation.

SgAsmRegisterReferenceExpression* Rose::BinaryAnalysis::DisassemblerMips::makeShadowRegister ( unsigned  regnum)

Create a new register reference for a shadow GPR.

SgAsmIntegerValueExpression* Rose::BinaryAnalysis::DisassemblerMips::makeImmediate8 ( unsigned  value,
size_t  bit_offset,
size_t  nbits 
)

Create a new 8-bit value expression from an 8-bit value.

The bit_offset and nbits indicate where the value originally came from in the instruction.

SgAsmIntegerValueExpression* Rose::BinaryAnalysis::DisassemblerMips::makeImmediate16 ( unsigned  value,
size_t  bit_offset,
size_t  nbits 
)

Create a new 16-bit value expression from a 16-bit value.

The bit_offset and nbits indicate where the value originally came from in the instruction.

SgAsmIntegerValueExpression* Rose::BinaryAnalysis::DisassemblerMips::makeImmediate32 ( unsigned  value,
size_t  bit_offset,
size_t  nbits 
)

Create a new 32-bit value expression from a 32-bit value.

The bit_offset and nbits indicate where the value originally came from in the instruction.

SgAsmIntegerValueExpression* Rose::BinaryAnalysis::DisassemblerMips::makeBranchTargetRelative ( unsigned  offset16,
size_t  bit_offset,
size_t  nbits 
)

Create a 32-bit PC-relative branch target address from a 16-bit offset.

The bit_offset and nbits indicate where the value originally came from in the instruction (usually 0 and 16, respectively). The return address is the address of the delay slot plus four times the signed offset16.

SgAsmIntegerValueExpression* Rose::BinaryAnalysis::DisassemblerMips::makeBranchTargetAbsolute ( unsigned  insn_index,
size_t  bit_offset,
size_t  nbits 
)

Create a 32-bit branch address from an instruction index value.

The returned value is the insn_index (nbits wide) multiplied by four and then combined with the address of the delay slot. They are combined such that the low-order nbits+2 bits are from the product and the upper bits are from the delay slot address.

SgAsmBinaryAdd* Rose::BinaryAnalysis::DisassemblerMips::makeRegisterOffset ( unsigned  gprnum,
unsigned  offset16 
)

Build an expression for an offset from a register.

The return value is GPR[regnum]+signExtend(offset) expressed as an SgAsmBinaryAdd expression whose first operand is the register reference expression and second operand is the sign-extended offset.

SgAsmBinaryAdd* Rose::BinaryAnalysis::DisassemblerMips::makeRegisterIndexed ( unsigned  base_gprnum,
unsigned  index_gprnum 
)

Build a register index expression.

The returned value is makeRegister(base_gprnum)+makeRegister(index_gprnum).

SgAsmMemoryReferenceExpression* Rose::BinaryAnalysis::DisassemblerMips::makeMemoryReference ( SgAsmExpression addr,
SgAsmType type 
)

Build a memory reference expression.

Member Data Documentation

std::vector<Mips32*> Rose::BinaryAnalysis::DisassemblerMips::idis_table
protected

Table of instruction-specific disassemblers.

This is the table of instruction-specific disassemblers consulted by find_idis().

Definition at line 139 of file DisassemblerMips.h.

rose_addr_t Rose::BinaryAnalysis::DisassemblerMips::insn_va
protected

Address of instruction currently being disassembled.

This is set each time disassembleOne() is called.

Definition at line 142 of file DisassemblerMips.h.

Referenced by get_ip().


The documentation for this class was generated from the following file: