ROSE  0.9.9.139
DisassemblerMips.h
1 /* Disassembly specific to the MIPS architecture */
2 #ifndef ROSE_DISASSEMBLER_MIPS_H
3 #define ROSE_DISASSEMBLER_MIPS_H
4 
5 #include "Disassembler.h"
6 #include "InstructionEnumsMips.h"
7 #include "sageBuilderAsm.h"
8 
9 namespace Rose {
10 namespace BinaryAnalysis {
11 
13 public:
17  explicit DisassemblerMips(ByteOrder::Endianness sex = ByteOrder::ORDER_MSB) { init(sex); }
18 
19  virtual DisassemblerMips *clone() const ROSE_OVERRIDE { return new DisassemblerMips(*this); }
20  virtual bool canDisassemble(SgAsmGenericHeader*) const ROSE_OVERRIDE;
21  virtual SgAsmInstruction *disassembleOne(const MemoryMap::Ptr&, rose_addr_t start_va,
22  AddressSet *successors=NULL) ROSE_OVERRIDE;
23  virtual SgAsmInstruction *makeUnknownInstruction(const Disassembler::Exception&) ROSE_OVERRIDE;
24  virtual Unparser::BasePtr unparser() const ROSE_OVERRIDE;
25 
32  class Mips32 {
33  public:
34  enum Architecture { Release1, Release2, Release3, Micro };
35  Mips32(Architecture arch, unsigned match, unsigned mask): arch(arch), match(match), mask(mask) {}
36  virtual ~Mips32() {}
37  Architecture arch; // architecture where this instruction was introduced
38  unsigned match; // value of compared bits
39  unsigned mask; // bits of 'match' that will be compared
40  typedef DisassemblerMips D;
41  virtual SgAsmMipsInstruction *operator()(D *d, unsigned insn_bits) = 0;
42  };
43 
47  Mips32 *find_idis(unsigned insn_bits);
48 
52  void insert_idis(Mips32*, bool replace=false);
53 
58  SgAsmMipsInstruction *disassemble_insn(unsigned insn_bits);
59 
60 
62  // The following functions are used by the various instruction-specific Mips32 subclasses.
63 
65  rose_addr_t get_ip() const { return insn_va; }
66 
68  SgAsmMipsInstruction *makeInstruction(MipsInstructionKind, const std::string &mnemonic,
69  SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL,
70  SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL);
71 
74 
77 
79  SgAsmRegisterReferenceExpression *makeCp0Register(unsigned regnum, unsigned sel);
80 
83 
88 
91 
94 
97 
100  SgAsmIntegerValueExpression *makeImmediate8(unsigned value, size_t bit_offset, size_t nbits);
101 
104  SgAsmIntegerValueExpression *makeImmediate16(unsigned value, size_t bit_offset, size_t nbits);
105 
108  SgAsmIntegerValueExpression *makeImmediate32(unsigned value, size_t bit_offset, size_t nbits);
109 
113  SgAsmIntegerValueExpression *makeBranchTargetRelative(unsigned offset16, size_t bit_offset, size_t nbits);
114 
118  SgAsmIntegerValueExpression *makeBranchTargetAbsolute(unsigned insn_index, size_t bit_offset, size_t nbits);
119 
123  SgAsmBinaryAdd *makeRegisterOffset(unsigned gprnum, unsigned offset16);
124 
126  SgAsmBinaryAdd *makeRegisterIndexed(unsigned base_gprnum, unsigned index_gprnum);
127 
130 
132 
133 protected:
134  void init(ByteOrder::Endianness);
135 
136 protected:
139  std::vector<Mips32*> idis_table;
140 
142  rose_addr_t insn_va;
143 };
144 
145 } // namespace
146 } // namespace
147 
148 #endif
SgAsmIntegerValueExpression * makeImmediate8(unsigned value, size_t bit_offset, size_t nbits)
Create a new 8-bit value expression from an 8-bit value.
DisassemblerMips(ByteOrder::Endianness sex=ByteOrder::ORDER_MSB)
Create a MIPS disassembler.
SgAsmRegisterReferenceExpression * makeShadowRegister(unsigned regnum)
Create a new register reference for a shadow GPR.
Expression that adds two operands.
Base class for references to a machine register.
SgAsmMipsInstruction * disassemble_insn(unsigned insn_bits)
Disassemble a single instruction.
rose_addr_t get_ip() const
Obtain the virtual address for the instruction being disassembled.
SgAsmMipsInstruction * makeInstruction(MipsInstructionKind, const std::string &mnemonic, SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL, SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL)
Create a new instruction.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &, rose_addr_t start_va, AddressSet *successors=NULL) ROSE_OVERRIDE
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
Base class for machine instructions.
SgAsmRegisterReferenceExpression * makeCp0Register(unsigned regnum, unsigned sel)
Create a new register reference for Coprocessor 0.
SgAsmRegisterReferenceExpression * makeFpccRegister(unsigned cc)
Create a new floating point condition flag register reference expression.
SgAsmIntegerValueExpression * makeImmediate16(unsigned value, size_t bit_offset, size_t nbits)
Create a new 16-bit value expression from a 16-bit value.
void insert_idis(Mips32 *, bool replace=false)
Insert an instruction-specific disassembler.
Main namespace for the ROSE library.
SgAsmBinaryAdd * makeRegisterOffset(unsigned gprnum, unsigned offset16)
Build an expression for an offset from a register.
SgAsmIntegerValueExpression * makeBranchTargetAbsolute(unsigned insn_index, size_t bit_offset, size_t nbits)
Create a 32-bit branch address from an instruction index value.
Interface for disassembling a single instruction.
Reference to memory locations.
SgAsmRegisterReferenceExpression * makeHwRegister(unsigned regnum)
Create a new register reference for a hardware register.
Base class for container file headers.
Base class for integer values.
SgAsmIntegerValueExpression * makeImmediate32(unsigned value, size_t bit_offset, size_t nbits)
Create a new 32-bit value expression from a 32-bit value.
An efficient mapping from an address space to stored data.
Definition: MemoryMap.h:96
Base class for expressions.
SgAsmMemoryReferenceExpression * makeMemoryReference(SgAsmExpression *addr, SgAsmType *type)
Build a memory reference expression.
SgAsmRegisterReferenceExpression * makeCp2Register(unsigned regnum)
Create a new register reference for Coprocessor 2.
SgAsmRegisterReferenceExpression * makeCp2ccRegister(unsigned cc)
Create a new register reference for a COP2 condition code.
Represents one MIPS machine instruction.
Base class for binary types.
SgAsmBinaryAdd * makeRegisterIndexed(unsigned base_gprnum, unsigned index_gprnum)
Build a register index expression.
SgAsmIntegerValueExpression * makeBranchTargetRelative(unsigned offset16, size_t bit_offset, size_t nbits)
Create a 32-bit PC-relative branch target address from a 16-bit offset.
rose_addr_t insn_va
Address of instruction currently being disassembled.
virtual Unparser::BasePtr unparser() const ROSE_OVERRIDE
Unparser.
virtual SgAsmInstruction * makeUnknownInstruction(const Disassembler::Exception &) ROSE_OVERRIDE
Makes an unknown instruction from an exception.
SgAsmRegisterReferenceExpression * makeFpRegister(unsigned regnum)
Create a new floating point register reference expression.
virtual bool canDisassemble(SgAsmGenericHeader *) const ROSE_OVERRIDE
Predicate determining the suitability of a disassembler for a specific file header.
Mips32 * find_idis(unsigned insn_bits)
Find an instruction-specific disassembler.
Virtual base class for instruction disassemblers.
Definition: Disassembler.h:41
SgAsmRegisterReferenceExpression * makeRegister(unsigned regnum)
Create a new general purpose register reference expression.
virtual DisassemblerMips * clone() const ROSE_OVERRIDE
Creates a new copy of a disassembler.
std::set< rose_addr_t > AddressSet
An AddressSet contains virtual addresses (alternatively, relative virtual addresses) for such things ...
Definition: Disassembler.h:82
std::vector< Mips32 * > idis_table
Table of instruction-specific disassemblers.