ROSE  0.11.2.0
DisassemblerMips.h
1 /* Disassembly specific to the MIPS architecture */
2 #ifndef ROSE_DISASSEMBLER_MIPS_H
3 #define ROSE_DISASSEMBLER_MIPS_H
4 
5 #include "Disassembler.h"
6 #ifdef ROSE_BUILD_BINARY_ANALYSIS_SUPPORT
7 
8 #include "InstructionEnumsMips.h"
9 #include "SageBuilderAsm.h"
10 
11 namespace Rose {
12 namespace BinaryAnalysis {
13 
15 public:
19  explicit DisassemblerMips(ByteOrder::Endianness sex = ByteOrder::ORDER_MSB) { init(sex); }
20 
21  virtual DisassemblerMips *clone() const ROSE_OVERRIDE { return new DisassemblerMips(*this); }
22  virtual bool canDisassemble(SgAsmGenericHeader*) const ROSE_OVERRIDE;
23  virtual SgAsmInstruction *disassembleOne(const MemoryMap::Ptr&, rose_addr_t start_va,
24  AddressSet *successors=NULL) ROSE_OVERRIDE;
25  virtual SgAsmInstruction *makeUnknownInstruction(const Disassembler::Exception&) ROSE_OVERRIDE;
26  SgAsmMipsInstruction *makeUnknownInstruction(rose_addr_t insn_va, unsigned opcode) const;
27  virtual Unparser::BasePtr unparser() const ROSE_OVERRIDE;
28 
35  class Mips32 {
36  public:
37  enum Architecture { Release1, Release2, Release3, Micro };
38  Mips32(Architecture arch, unsigned match, unsigned mask): arch(arch), match(match), mask(mask) {}
39  virtual ~Mips32() {}
40  Architecture arch; // architecture where this instruction was introduced
41  unsigned match; // value of compared bits
42  unsigned mask; // bits of 'match' that will be compared
43  typedef DisassemblerMips D;
44  virtual SgAsmMipsInstruction *operator()(rose_addr_t insn_va, const D *d, unsigned insn_bits) = 0;
45  };
46 
50  Mips32 *find_idis(rose_addr_t insn_va, unsigned insn_bits) const;
51 
55  void insert_idis(Mips32*, bool replace=false);
56 
61  SgAsmMipsInstruction *disassemble_insn(rose_addr_t insn_va, unsigned insn_bits) const;
62 
63 
65  // The following functions are used by the various instruction-specific Mips32 subclasses.
66 
68  SgAsmMipsInstruction *makeInstruction(rose_addr_t insn_va, MipsInstructionKind, const std::string &mnemonic,
69  SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL,
70  SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL) const;
71 
73  SgAsmRegisterReferenceExpression *makeRegister(rose_addr_t insn_va, unsigned regnum) const;
74 
76  SgAsmRegisterReferenceExpression *makeFpRegister(rose_addr_t insn_va, unsigned regnum) const;
77 
79  SgAsmRegisterReferenceExpression *makeCp0Register(rose_addr_t insn_va, unsigned regnum, unsigned sel) const;
80 
82  SgAsmRegisterReferenceExpression *makeCp2Register(unsigned regnum) const;
83 
87  SgAsmRegisterReferenceExpression *makeFpccRegister(rose_addr_t insn_va, unsigned cc) const;
88 
91 
93  SgAsmRegisterReferenceExpression *makeHwRegister(unsigned regnum) const;
94 
96  SgAsmRegisterReferenceExpression *makeShadowRegister(rose_addr_t insn_va, unsigned regnum) const;
97 
100  SgAsmIntegerValueExpression *makeImmediate8(unsigned value, size_t bit_offset, size_t nbits) const;
101 
104  SgAsmIntegerValueExpression *makeImmediate16(unsigned value, size_t bit_offset, size_t nbits) const;
105 
108  SgAsmIntegerValueExpression *makeImmediate32(unsigned value, size_t bit_offset, size_t nbits) const;
109 
113  SgAsmIntegerValueExpression *makeBranchTargetRelative(rose_addr_t insn_va, unsigned offset16, size_t bit_offset,
114  size_t nbits) const;
115 
119  SgAsmIntegerValueExpression *makeBranchTargetAbsolute(rose_addr_t insn_va, unsigned insn_index, size_t bit_offset,
120  size_t nbits) const;
121 
125  SgAsmBinaryAdd *makeRegisterOffset(rose_addr_t insn_va, unsigned gprnum, unsigned offset16) const;
126 
128  SgAsmBinaryAdd *makeRegisterIndexed(rose_addr_t insn_va, unsigned base_gprnum, unsigned index_gprnum) const;
129 
132 
134 
135 protected:
136  void init(ByteOrder::Endianness);
137 
138 protected:
141  std::vector<Mips32*> idis_table;
142 };
143 
144 } // namespace
145 } // namespace
146 
147 #endif
148 #endif
SgAsmRegisterReferenceExpression * makeHwRegister(unsigned regnum) const
Create a new register reference for a hardware register.
Mips32 * find_idis(rose_addr_t insn_va, unsigned insn_bits) const
Find an instruction-specific disassembler.
DisassemblerMips(ByteOrder::Endianness sex=ByteOrder::ORDER_MSB)
Create a MIPS disassembler.
Expression that adds two operands.
SgAsmIntegerValueExpression * makeImmediate16(unsigned value, size_t bit_offset, size_t nbits) const
Create a new 16-bit value expression from a 16-bit value.
SgAsmIntegerValueExpression * makeBranchTargetRelative(rose_addr_t insn_va, unsigned offset16, size_t bit_offset, size_t nbits) const
Create a 32-bit PC-relative branch target address from a 16-bit offset.
SgAsmIntegerValueExpression * makeImmediate32(unsigned value, size_t bit_offset, size_t nbits) const
Create a new 32-bit value expression from a 32-bit value.
Base class for references to a machine register.
SgAsmBinaryAdd * makeRegisterIndexed(rose_addr_t insn_va, unsigned base_gprnum, unsigned index_gprnum) const
Build a register index expression.
SgAsmRegisterReferenceExpression * makeShadowRegister(rose_addr_t insn_va, unsigned regnum) const
Create a new register reference for a shadow GPR.
SgAsmRegisterReferenceExpression * makeCp2ccRegister(unsigned cc) const
Create a new register reference for a COP2 condition code.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &, rose_addr_t start_va, AddressSet *successors=NULL) ROSE_OVERRIDE
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
Base class for machine instructions.
SgAsmRegisterReferenceExpression * makeCp0Register(rose_addr_t insn_va, unsigned regnum, unsigned sel) const
Create a new register reference for Coprocessor 0.
SgAsmMipsInstruction * makeInstruction(rose_addr_t insn_va, MipsInstructionKind, const std::string &mnemonic, SgAsmExpression *arg1=NULL, SgAsmExpression *arg2=NULL, SgAsmExpression *arg3=NULL, SgAsmExpression *arg4=NULL) const
Create a new instruction.
void insert_idis(Mips32 *, bool replace=false)
Insert an instruction-specific disassembler.
Main namespace for the ROSE library.
SgAsmRegisterReferenceExpression * makeFpccRegister(rose_addr_t insn_va, unsigned cc) const
Create a new floating point condition flag register reference expression.
SgAsmRegisterReferenceExpression * makeFpRegister(rose_addr_t insn_va, unsigned regnum) const
Create a new floating point register reference expression.
SgAsmIntegerValueExpression * makeBranchTargetAbsolute(rose_addr_t insn_va, unsigned insn_index, size_t bit_offset, size_t nbits) const
Create a 32-bit branch address from an instruction index value.
SgAsmRegisterReferenceExpression * makeCp2Register(unsigned regnum) const
Create a new register reference for Coprocessor 2.
Interface for disassembling a single instruction.
SgAsmBinaryAdd * makeRegisterOffset(rose_addr_t insn_va, unsigned gprnum, unsigned offset16) const
Build an expression for an offset from a register.
Reference to memory locations.
Base class for container file headers.
SgAsmMemoryReferenceExpression * makeMemoryReference(SgAsmExpression *addr, SgAsmType *type) const
Build a memory reference expression.
Base class for integer values.
An efficient mapping from an address space to stored data.
Definition: MemoryMap.h:112
Base class for expressions.
MipsInstructionKind
Kinds of MIPS instructions.
Represents one MIPS machine instruction.
Base class for binary types.
SgAsmMipsInstruction * disassemble_insn(rose_addr_t insn_va, unsigned insn_bits) const
Disassemble a single instruction.
virtual Unparser::BasePtr unparser() const ROSE_OVERRIDE
Unparser.
virtual SgAsmInstruction * makeUnknownInstruction(const Disassembler::Exception &) ROSE_OVERRIDE
Makes an unknown instruction from an exception.
virtual bool canDisassemble(SgAsmGenericHeader *) const ROSE_OVERRIDE
Predicate determining the suitability of a disassembler for a specific file header.
SgAsmRegisterReferenceExpression * makeRegister(rose_addr_t insn_va, unsigned regnum) const
Create a new general purpose register reference expression.
Base class for all ROSE exceptions.
Definition: RoseException.h:9
Virtual base class for instruction disassemblers.
Definition: Disassembler.h:50
SgAsmIntegerValueExpression * makeImmediate8(unsigned value, size_t bit_offset, size_t nbits) const
Create a new 8-bit value expression from an 8-bit value.
virtual DisassemblerMips * clone() const ROSE_OVERRIDE
Creates a new copy of a disassembler.
std::vector< Mips32 * > idis_table
Table of instruction-specific disassemblers.