ROSE  0.9.9.139
Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86 Class Reference

Description

Definition at line 23 of file DispatcherX86.h.

Inheritance diagram for Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86:
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Collaboration diagram for Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86:
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Public Types

enum  AccessMode {
  READ_REGISTER,
  PEEK_REGISTER
}
 
typedef BaseSemantics::Dispatcher Super
 
- Public Types inherited from Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher
typedef DispatcherPtr Ptr
 Shared-ownership pointer for a Dispatcher object. More...
 

Public Member Functions

void iproc_init ()
 Loads the iproc table with instruction processing functors. More...
 
void regcache_init ()
 Load the cached register descriptors. More...
 
void memory_init ()
 Make sure memory is set up correctly. More...
 
virtual BaseSemantics::DispatcherPtr create (const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth=0, const RegisterDictionary *regs=NULL) const ROSE_OVERRIDE
 Virtual constructor. More...
 
virtual void set_register_dictionary (const RegisterDictionary *regdict) ROSE_OVERRIDE
 Access the register dictionary. More...
 
virtual RegisterDictionary::RegisterDescriptors get_usual_registers () const
 Get list of common registers. More...
 
virtual RegisterDescriptor instructionPointerRegister () const ROSE_OVERRIDE
 Returns the instruction pointer register. More...
 
virtual RegisterDescriptor stackPointerRegister () const ROSE_OVERRIDE
 Returns the stack pointer register. More...
 
virtual int iproc_key (SgAsmInstruction *insn_) const ROSE_OVERRIDE
 Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table. More...
 
virtual void write (SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits=0) ROSE_OVERRIDE
 Writes to an L-value expression. More...
 
virtual BaseSemantics::SValuePtr readRegister (RegisterDescriptor, AccessMode mode=READ_REGISTER)
 Architecture-specific read from register. More...
 
virtual void writeRegister (RegisterDescriptor, const BaseSemantics::SValuePtr &result)
 Architecture-specific write to register. More...
 
virtual void setFlagsForResult (const BaseSemantics::SValuePtr &result)
 Set parity, sign, and zero flags appropriate for result value. More...
 
virtual void setFlagsForResult (const BaseSemantics::SValuePtr &result, const BaseSemantics::SValuePtr &cond)
 Conditionally set parity, sign, and zero flags appropriate for result value. More...
 
virtual BaseSemantics::SValuePtr parity (const BaseSemantics::SValuePtr &v)
 Returns true if byte v has an even number of bits set; false for an odd number.
 
virtual BaseSemantics::SValuePtr invertMaybe (const BaseSemantics::SValuePtr &value, bool maybe)
 Conditionally invert the bits of value. More...
 
virtual BaseSemantics::SValuePtr greaterOrEqualToTen (const BaseSemantics::SValuePtr &value)
 Determines whether value is greater than or equal to ten. More...
 
virtual BaseSemantics::SValuePtr flagsCombo (X86InstructionKind k)
 Return a Boolean for the specified flag combo for an instruction. More...
 
virtual BaseSemantics::SValuePtr repEnter (X86RepeatPrefix)
 Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction. More...
 
virtual void repLeave (X86RepeatPrefix, const BaseSemantics::SValuePtr &in_loop, rose_addr_t insn_va, bool honorZeroFlag)
 Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction. More...
 
virtual BaseSemantics::SValuePtr doIncOperation (const BaseSemantics::SValuePtr &a, bool dec, bool setCarry)
 Increments or decrements a value and adjusts flags. More...
 
virtual BaseSemantics::SValuePtr doRotateOperation (X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &total_rotate, size_t rotateSignificantBits)
 Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes. More...
 
virtual BaseSemantics::SValuePtr doShiftOperation (X86InstructionKind kind, const BaseSemantics::SValuePtr &operand, const BaseSemantics::SValuePtr &source_bits, const BaseSemantics::SValuePtr &total_shift, size_t shiftSignificantBits)
 Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes. More...
 
virtual void pushFloatingPoint (const BaseSemantics::SValuePtr &valueToPush)
 Push floating-point value onto FP stack. More...
 
virtual BaseSemantics::SValuePtr readFloatingPointStack (size_t position)
 Read a value from the floating point stack. More...
 
virtual void popFloatingPoint ()
 Pop the top item from the floating point stack. More...
 
virtual BaseSemantics::SValuePtr fixMemoryAddress (const BaseSemantics::SValuePtr &address) const
 Extend or truncate value to propert memory address width. More...
 
virtual BaseSemantics::SValuePtr saturateSignedToUnsigned (const BaseSemantics::SValuePtr &, size_t narrowerWidth)
 Convert a signed value to a narrower unsigned type. More...
 
virtual BaseSemantics::SValuePtr saturateSignedToSigned (const BaseSemantics::SValuePtr &, size_t narrowerWidth)
 Convert a signed value to a narrower signed type. More...
 
virtual BaseSemantics::SValuePtr saturateUnsignedToUnsigned (const BaseSemantics::SValuePtr &, size_t narrowerWidth)
 Convert an unsigned value to a narrower unsigned type. More...
 
X86InstructionSize processorMode () const
 CPU mode of operation.
 
void processorMode (X86InstructionSize m)
 CPU mode of operation.
 
virtual BaseSemantics::SValuePtr doAddOperation (BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn)
 Adds two values and adjusts flags. More...
 
virtual BaseSemantics::SValuePtr doAddOperation (BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, bool invertCarries, const BaseSemantics::SValuePtr &carryIn, const BaseSemantics::SValuePtr &cond)
 Adds two values and adjusts flags. More...
 
- Public Member Functions inherited from Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher
virtual void processInstruction (SgAsmInstruction *insn)
 Process a single instruction. More...
 
virtual InsnProcessoriproc_lookup (SgAsmInstruction *insn)
 Lookup the processor for an instruction. More...
 
virtual void iproc_replace (SgAsmInstruction *insn, InsnProcessor *iproc)
 Replace an instruction processor with another. More...
 
virtual void iproc_set (int key, InsnProcessor *iproc)
 Set an iproc table entry to the specified value. More...
 
virtual InsnProcessoriproc_get (int key)
 Obtain an iproc table entry for the specified key. More...
 
virtual RiscOperatorsPtr get_operators () const
 Get a pointer to the RISC operators object. More...
 
virtual StatePtr currentState () const
 Get a pointer to the state object. More...
 
virtual StatePtr get_state () const ROSE_DEPRECATED("use currentState instead")
 
virtual SValuePtr protoval () const
 Return the prototypical value. More...
 
virtual SValuePtr get_protoval () const ROSE_DEPRECATED("use protoval instead")
 
virtual SgAsmInstructioncurrentInstruction () const
 Returns the instruction that is being processed. More...
 
virtual SgAsmInstructionget_insn () const ROSE_DEPRECATED("use currentInstruction instead")
 
virtual SValuePtr undefined_ (size_t nbits) const
 Return a new undefined semantic value. More...
 
virtual SValuePtr unspecified_ (size_t nbits) const
 
virtual SValuePtr number_ (size_t nbits, uint64_t number) const
 Return a semantic value representing a number. More...
 
virtual RegisterDescriptor findRegister (const std::string &regname, size_t nbits=0, bool allowMissing=false) const
 Lookup a register by name. More...
 
virtual void advanceInstructionPointer (SgAsmInstruction *)
 Update the instruction pointer register. More...
 
virtual RegisterDescriptor segmentRegister (SgAsmMemoryReferenceExpression *)
 Returns a register descriptor for the segment part of a memory reference expression. More...
 
virtual void incrementRegisters (SgAsmExpression *)
 Increment all auto-increment registers in the expression. More...
 
virtual void decrementRegisters (SgAsmExpression *)
 Decrement all auto-decrement registers in the expression. More...
 
virtual SValuePtr effectiveAddress (SgAsmExpression *, size_t nbits=0)
 Returns a memory address by evaluating the address expression. More...
 
virtual SValuePtr read (SgAsmExpression *, size_t value_nbits=0, size_t addr_nbits=0)
 Reads an R-value expression. More...
 
virtual const RegisterDictionaryget_register_dictionary () const
 Access the register dictionary. More...
 
size_t addressWidth () const
 Property: Width of memory addresses. More...
 
void addressWidth (size_t nbits)
 Property: Width of memory addresses. More...
 
bool autoResetInstructionPointer () const
 Property: Reset instruction pointer register for each instruction. More...
 
void autoResetInstructionPointer (bool b)
 Property: Reset instruction pointer register for each instruction. More...
 

Static Public Member Functions

static DispatcherX86Ptr instance ()
 Construct a prototypical dispatcher. More...
 
static DispatcherX86Ptr instance (size_t addrWidth, const RegisterDictionary *regs=NULL)
 Construct a prototyipcal dispatcher. More...
 
static DispatcherX86Ptr instance (const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs=NULL)
 Constructor. More...
 
static DispatcherX86Ptr promote (const BaseSemantics::DispatcherPtr &d)
 Dynamic cast to a DispatcherX86Ptr with assertion. More...
 

Public Attributes

RegisterDescriptor REG_anyAX
 Cached register. More...
 
RegisterDescriptor REG_anyBX
 Cached register. More...
 
RegisterDescriptor REG_anyCX
 Cached register. More...
 
RegisterDescriptor REG_anyDX
 Cached register. More...
 
RegisterDescriptor REG_RAX
 Cached register. More...
 
RegisterDescriptor REG_RBX
 Cached register. More...
 
RegisterDescriptor REG_RCX
 Cached register. More...
 
RegisterDescriptor REG_RDX
 Cached register. More...
 
RegisterDescriptor REG_EAX
 Cached register. More...
 
RegisterDescriptor REG_EBX
 Cached register. More...
 
RegisterDescriptor REG_ECX
 Cached register. More...
 
RegisterDescriptor REG_EDX
 Cached register. More...
 
RegisterDescriptor REG_AX
 Cached register. More...
 
RegisterDescriptor REG_BX
 Cached register. More...
 
RegisterDescriptor REG_CX
 Cached register. More...
 
RegisterDescriptor REG_DX
 Cached register. More...
 
RegisterDescriptor REG_AL
 Cached register. More...
 
RegisterDescriptor REG_BL
 Cached register. More...
 
RegisterDescriptor REG_CL
 Cached register. More...
 
RegisterDescriptor REG_DL
 Cached register. More...
 
RegisterDescriptor REG_AH
 Cached register. More...
 
RegisterDescriptor REG_BH
 Cached register. More...
 
RegisterDescriptor REG_CH
 Cached register. More...
 
RegisterDescriptor REG_DH
 Cached register. More...
 
RegisterDescriptor REG_R8
 Cached register. More...
 
RegisterDescriptor REG_R9
 Cached register. More...
 
RegisterDescriptor REG_R10
 Cached register. More...
 
RegisterDescriptor REG_R11
 Cached register. More...
 
RegisterDescriptor REG_R12
 Cached register. More...
 
RegisterDescriptor REG_R13
 Cached register. More...
 
RegisterDescriptor REG_R14
 Cached register. More...
 
RegisterDescriptor REG_R15
 Cached register. More...
 
RegisterDescriptor REG_anyDI
 Cached register. More...
 
RegisterDescriptor REG_anySI
 Cached register. More...
 
RegisterDescriptor REG_anySP
 Cached register. More...
 
RegisterDescriptor REG_anyBP
 Cached register. More...
 
RegisterDescriptor REG_anyIP
 Cached register. More...
 
RegisterDescriptor REG_RDI
 Cached register. More...
 
RegisterDescriptor REG_RSI
 Cached register. More...
 
RegisterDescriptor REG_RSP
 Cached register. More...
 
RegisterDescriptor REG_RBP
 Cached register. More...
 
RegisterDescriptor REG_RIP
 Cached register. More...
 
RegisterDescriptor REG_EDI
 Cached register. More...
 
RegisterDescriptor REG_ESI
 Cached register. More...
 
RegisterDescriptor REG_ESP
 Cached register. More...
 
RegisterDescriptor REG_EBP
 Cached register. More...
 
RegisterDescriptor REG_EIP
 Cached register. More...
 
RegisterDescriptor REG_DI
 Cached register. More...
 
RegisterDescriptor REG_SI
 Cached register. More...
 
RegisterDescriptor REG_SP
 Cached register. More...
 
RegisterDescriptor REG_BP
 Cached register. More...
 
RegisterDescriptor REG_IP
 Cached register. More...
 
RegisterDescriptor REG_CS
 Cached register. More...
 
RegisterDescriptor REG_DS
 Cached register. More...
 
RegisterDescriptor REG_ES
 Cached register. More...
 
RegisterDescriptor REG_SS
 Cached register. More...
 
RegisterDescriptor REG_FS
 Cached register. More...
 
RegisterDescriptor REG_GS
 Cached register. More...
 
RegisterDescriptor REG_anyFLAGS
 Cached register. More...
 
RegisterDescriptor REG_RFLAGS
 Cached register. More...
 
RegisterDescriptor REG_EFLAGS
 Cached register. More...
 
RegisterDescriptor REG_FLAGS
 Cached register. More...
 
RegisterDescriptor REG_AF
 Cached register. More...
 
RegisterDescriptor REG_CF
 Cached register. More...
 
RegisterDescriptor REG_DF
 Cached register. More...
 
RegisterDescriptor REG_OF
 Cached register. More...
 
RegisterDescriptor REG_PF
 Cached register. More...
 
RegisterDescriptor REG_SF
 Cached register. More...
 
RegisterDescriptor REG_TF
 Cached register. More...
 
RegisterDescriptor REG_ZF
 Cached register. More...
 
RegisterDescriptor REG_ST0
 Cached register. More...
 
RegisterDescriptor REG_FPSTATUS
 Cached register. More...
 
RegisterDescriptor REG_FPSTATUS_TOP
 Cached register. More...
 
RegisterDescriptor REG_FPCTL
 Cached register. More...
 
RegisterDescriptor REG_MXCSR
 Cached register. More...
 

Protected Member Functions

 DispatcherX86 (size_t addrWidth, const RegisterDictionary *regs)
 
 DispatcherX86 (const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
 
- Protected Member Functions inherited from Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher
 Dispatcher (size_t addrWidth, const RegisterDictionary *regs)
 
 Dispatcher (const RiscOperatorsPtr &ops, size_t addrWidth, const RegisterDictionary *regs)
 

Protected Attributes

X86InstructionSize processorMode_
 
- Protected Attributes inherited from Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher
RiscOperatorsPtr operators
 
const RegisterDictionaryregdict
 See set_register_dictionary(). More...
 
size_t addrWidth_
 Width of memory addresses in bits. More...
 
bool autoResetInstructionPointer_
 Reset instruction pointer register for each instruction. More...
 
InsnProcessors iproc_table
 

Additional Inherited Members

- Protected Types inherited from Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher
typedef std::vector< InsnProcessor * > InsnProcessors
 

Member Function Documentation

void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::iproc_init ( )

Loads the iproc table with instruction processing functors.

This normally happens from the constructor.

void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::regcache_init ( )

Load the cached register descriptors.

This happens at construction and on set_register_dictionary() calls.

void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::memory_init ( )

Make sure memory is set up correctly.

For instance, byte order should be little endian.

static DispatcherX86Ptr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::instance ( )
inlinestatic

Construct a prototypical dispatcher.

The only thing this dispatcher can be used for is to create another dispatcher with the virtual create method.

Definition at line 117 of file DispatcherX86.h.

Referenced by create(), and Rose::BinaryAnalysis::InstructionSemantics2::LlvmSemantics::Transcoder::instanceX86().

static DispatcherX86Ptr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::instance ( size_t  addrWidth,
const RegisterDictionary regs = NULL 
)
inlinestatic

Construct a prototyipcal dispatcher.

Construct a prototypical dispatcher with a specified address size. The only thing this dispatcher can be used for is to create another dispatcher with the virtual create method.

Definition at line 123 of file DispatcherX86.h.

static DispatcherX86Ptr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::instance ( const BaseSemantics::RiscOperatorsPtr ops,
size_t  addrWidth,
const RegisterDictionary regs = NULL 
)
inlinestatic

Constructor.

Definition at line 128 of file DispatcherX86.h.

virtual BaseSemantics::DispatcherPtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::create ( const BaseSemantics::RiscOperatorsPtr ops,
size_t  addrWidth = 0,
const RegisterDictionary regs = NULL 
) const
inlinevirtual
static DispatcherX86Ptr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::promote ( const BaseSemantics::DispatcherPtr d)
inlinestatic

Dynamic cast to a DispatcherX86Ptr with assertion.

Definition at line 144 of file DispatcherX86.h.

virtual void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::set_register_dictionary ( const RegisterDictionary regdict)
virtual

Access the register dictionary.

The register dictionary defines the set of registers over which the RISC operators may operate. This should be same registers (or superset thereof) whose values are stored in the machine state(s). This dictionary is used by the Dispatcher class to translate register names to register descriptors. For instance, to read from the "eax" register, the dispatcher will look up "eax" in its register dictionary and then pass that descriptor to the RiscOperators::readRegister operation. Register descriptors are also stored in instructions when the instruction is disassembled, so the dispatcher should probably be using the same registers as the disassembler, or a superset thereof.

The register dictionary should not be changed after a dispatcher is instantiated because the dispatcher's constructor may query the dictionary and cache the resultant register descriptors.

Reimplemented from Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher.

virtual RegisterDictionary::RegisterDescriptors Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::get_usual_registers ( ) const
virtual

Get list of common registers.

Returns a list of non-overlapping registers composed of the largest registers except using individual flags for the fields of the FLAGS/EFLAGS register.

virtual RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::instructionPointerRegister ( ) const
virtual

Returns the instruction pointer register.

Implements Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher.

virtual RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::stackPointerRegister ( ) const
virtual

Returns the stack pointer register.

Implements Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher.

virtual int Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::iproc_key ( SgAsmInstruction ) const
inlinevirtual

Given an instruction, return the InsnProcessor key that can be used as an index into the iproc_table.

Implements Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher.

Definition at line 167 of file DispatcherX86.h.

References SgAsmX86Instruction::get_kind().

virtual void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::write ( SgAsmExpression ,
const BaseSemantics::SValuePtr value,
size_t  addr_nbits = 0 
)
virtual

Writes to an L-value expression.

The expression can be a register or memory reference. The width of the address passed to lower-level memory access functions is specified by addr_nbits. If addr_nbits is zero then the natural width of the effective address is passed to lower level functions.

Reimplemented from Rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Dispatcher.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::readRegister ( RegisterDescriptor  ,
AccessMode  mode = READ_REGISTER 
)
virtual

Architecture-specific read from register.

Similar to RiscOperators::readRegister, but might do additional architecture-specific things.

virtual void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::writeRegister ( RegisterDescriptor  ,
const BaseSemantics::SValuePtr result 
)
virtual

Architecture-specific write to register.

Similar to RiscOperators::writeRegister, but might do additional architecture-specific things. For instance, writing to a 32-bit GPR such as "eax" on x86-64 will write zeros to the upper half of "rax".

virtual void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::setFlagsForResult ( const BaseSemantics::SValuePtr result)
virtual

Set parity, sign, and zero flags appropriate for result value.

virtual void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::setFlagsForResult ( const BaseSemantics::SValuePtr result,
const BaseSemantics::SValuePtr cond 
)
virtual

Conditionally set parity, sign, and zero flags appropriate for result value.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::invertMaybe ( const BaseSemantics::SValuePtr value,
bool  maybe 
)
virtual

Conditionally invert the bits of value.

The bits are inverted if maybe is true, otherwise value is returned.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::greaterOrEqualToTen ( const BaseSemantics::SValuePtr value)
virtual

Determines whether value is greater than or equal to ten.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::flagsCombo ( X86InstructionKind  k)
virtual

Return a Boolean for the specified flag combo for an instruction.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::repEnter ( X86RepeatPrefix  )
virtual

Enters a loop for a REP-, REPE-, or REPNE-prefixed instruction.

The return value is true if ECX is non-zero or the instruction doesn't have repeat prefix, and false otherwise. Use this in conjunction with repLeave().

virtual void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::repLeave ( X86RepeatPrefix  ,
const BaseSemantics::SValuePtr in_loop,
rose_addr_t  insn_va,
bool  honorZeroFlag 
)
virtual

Leave a loop for a REP-, REPE-, or REPNE-prefixed instruction.

The in_loop argument is the Boolean that indicates whether we just executed the instruction, and is usually the return value from the previous repEnter() call. If in_loop is false then this function is a no-op. Otherwise, the ECX register is decremented and, if it is non-zero and the repeat condition (true, equal, or not-equal) is satisified, then the EIP register is reset to the specified instruction address causing the instruction to be repeated. Use this in conjunction with repEnter(). The REP and REPE prefixes are shared, both represented by x86_repeat_repe, and we use the honorZeroFlag to decide whether the prefix is REP (false) or REPE (true).

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::doAddOperation ( BaseSemantics::SValuePtr  a,
BaseSemantics::SValuePtr  b,
bool  invertCarries,
const BaseSemantics::SValuePtr carryIn 
)
virtual

Adds two values and adjusts flags.

This method can be used for subtraction if b is two's complement and invertCarries is set. If cond is supplied, then the addition and flag adjustments are conditional.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::doAddOperation ( BaseSemantics::SValuePtr  a,
BaseSemantics::SValuePtr  b,
bool  invertCarries,
const BaseSemantics::SValuePtr carryIn,
const BaseSemantics::SValuePtr cond 
)
virtual

Adds two values and adjusts flags.

This method can be used for subtraction if b is two's complement and invertCarries is set. If cond is supplied, then the addition and flag adjustments are conditional.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::doIncOperation ( const BaseSemantics::SValuePtr a,
bool  dec,
bool  setCarry 
)
virtual

Increments or decrements a value and adjusts flags.

If dec is set then the value is decremented instead of incremented. If setCarry is set then the CF flag is affected.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::doRotateOperation ( X86InstructionKind  kind,
const BaseSemantics::SValuePtr operand,
const BaseSemantics::SValuePtr total_rotate,
size_t  rotateSignificantBits 
)
virtual

Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes.

The rotate amount is always 8 bits wide in the instruction, but the semantics mask off all but the low-order bits, keeping 5 bits in 32-bit mode and 6 bits in 64-bit mode (indicated by the rotateSignificantBits argument).

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::doShiftOperation ( X86InstructionKind  kind,
const BaseSemantics::SValuePtr operand,
const BaseSemantics::SValuePtr source_bits,
const BaseSemantics::SValuePtr total_shift,
size_t  shiftSignificantBits 
)
virtual

Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes.

The shift amount is always 8 bits wide in the instruction, but the semantics mask off all but the low-order bits, keeping 5 bits in 32-bit mode and 7 bits in 64-bit mode (indicated by the shiftSignificantBits argument). The semantics of SHL and SAL are identical (in fact, ROSE doesn't even define x86_sal). The source_bits argument contains the bits to be shifted into the result and is used only for SHRD and SHLD instructions.

virtual void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::pushFloatingPoint ( const BaseSemantics::SValuePtr valueToPush)
virtual

Push floating-point value onto FP stack.

Pushes the specified value onto the floating-point circular stack. The current top-of-stack is the REG_ST register, but whose minor number is the value stored in the REG_ST_TOP register. The value in REG_ST_TOP (which must be concrete) is decremented modulo eight before being used.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::readFloatingPointStack ( size_t  position)
virtual

Read a value from the floating point stack.

virtual void Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::popFloatingPoint ( )
virtual

Pop the top item from the floating point stack.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::fixMemoryAddress ( const BaseSemantics::SValuePtr address) const
virtual

Extend or truncate value to propert memory address width.

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::saturateSignedToUnsigned ( const BaseSemantics::SValuePtr ,
size_t  narrowerWidth 
)
virtual

Convert a signed value to a narrower unsigned type.

Returns the truncated source value except when the value cannot be represented in the narrower type, in which case the closest unsigned value is returned (zero or all bits set).

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::saturateSignedToSigned ( const BaseSemantics::SValuePtr ,
size_t  narrowerWidth 
)
virtual

Convert a signed value to a narrower signed type.

Returns the truncated source value except when the value cannot be represented by the narrower type, in which case the closest signed value is returned. The closest signed value is either 0b1000...0 (minimum signed value) or 0b0111...1 (maximum signed value).

virtual BaseSemantics::SValuePtr Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::saturateUnsignedToUnsigned ( const BaseSemantics::SValuePtr ,
size_t  narrowerWidth 
)
virtual

Convert an unsigned value to a narrower unsigned type.

Returns the truncated source value except when the value cannot be represented by the narrower type, in which case the closest unsigned value is returned.

Member Data Documentation

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anyAX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 39 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anyBX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 39 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anyCX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 39 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anyDX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 39 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RAX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 40 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RBX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 40 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RCX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 40 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RDX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 40 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_EAX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 41 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_EBX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 41 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_ECX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 41 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_EDX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 41 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_AX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 42 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_BX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 42 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_CX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 42 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_DX

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 42 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_AL

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 43 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_BL

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 43 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_CL

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 43 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_DL

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 43 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_AH

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 44 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_BH

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 44 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_CH

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 44 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_DH

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 44 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_R8

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 46 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_R9

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 46 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_R10

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 46 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_R11

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 46 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_R12

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 47 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_R13

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 47 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_R14

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 47 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_R15

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 47 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anyDI

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 49 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anySI

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 49 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anySP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 49 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anyBP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 49 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anyIP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 49 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RDI

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 50 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RSI

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 50 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RSP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 50 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RBP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 50 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RIP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 50 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_EDI

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 51 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_ESI

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 51 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_ESP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 51 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_EBP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 51 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_EIP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 51 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_DI

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 52 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_SI

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 52 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_SP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 52 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_BP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 52 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_IP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 52 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_CS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 54 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_DS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 54 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_ES

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 54 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_SS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 54 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_FS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 54 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_GS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 54 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_anyFLAGS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 56 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_RFLAGS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 56 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_EFLAGS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 56 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_FLAGS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 56 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_AF

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 57 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_CF

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 57 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_DF

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 57 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_OF

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 57 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_PF

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 57 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_SF

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 57 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_TF

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 57 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_ZF

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 57 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_ST0

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 59 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_FPSTATUS

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 59 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_FPSTATUS_TOP

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 59 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_FPCTL

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 59 of file DispatcherX86.h.

RegisterDescriptor Rose::BinaryAnalysis::InstructionSemantics2::DispatcherX86::REG_MXCSR

Cached register.

This register is cached so that there are not so many calls to Dispatcher::findRegister(). The register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()).

Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for 32-bit architectures, etc. The other register names have specific sizes–such as REG_EAX being 32 bits–and are defined only on architectures that support them.

Definition at line 59 of file DispatcherX86.h.


The documentation for this class was generated from the following file: