2#ifndef ROSE_BinaryAnalysis_Disassembler_Powerpc_H
3#define ROSE_BinaryAnalysis_Disassembler_Powerpc_H
4#include <featureTests.h>
5#ifdef ROSE_ENABLE_BINARY_ANALYSIS
6#include <Rose/BinaryAnalysis/Disassembler/Base.h>
8#include <Rose/BinaryAnalysis/Architecture/BasicTypes.h>
9#include <Rose/BinaryAnalysis/InstructionEnumsPowerpc.h>
11#include <SgAsmIntegerValueExpression.h>
13#include "integerOps.h"
14#include "SageBuilderAsm.h"
16#include <Sawyer/BitFlags.h>
19namespace BinaryAnalysis {
20namespace Disassembler {
33 State(): ip(0), insn(0) {}
36 PowerpcWordSize wordSize_;
39 bool strictReserved_ =
false;
79 class ExceptionPowerpc:
public Exception {
81 ExceptionPowerpc(
const std::string &mesg,
const State &state,
size_t bit=0);
85 makeRegister(State&, PowerpcRegisterClass reg_class,
int reg_number,
86 PowerpcConditionRegisterAccessGranularity reg_grainularity = powerpc_condreggranularity_whole,
93 bool is64bitInsn(PowerpcInstructionKind);
96 SgAsmPowerpcInstruction* makeInstructionWithoutOperands(uint64_t address, PowerpcInstructionKind, uint32_t insnBytes,
100 template <
size_t First,
size_t Last> uint64_t fld(State&)
const;
103 template<
size_t First,
size_t Last>
bool reservedOk(State&)
const;
106 bool AA(State &state)
const;
109 uint64_t BD(State &state)
const;
129 uint8_t L_sync(State &state)
const;
131 uint64_t LI(State &state)
const;
132 bool LK(State &state)
const;
138 bool OE(State &state)
const;
142 bool Rc(State &state)
const;
187 void startInstruction(State &state,
Address start_va, uint32_t c)
const;
Virtual base class for instruction disassemblers.
Exception thrown by the disassemblers.
size_t bit
Bit offset in instruction byte sequence where disassembly failed (bit/8 is the index into the "bytes"...
Disassembler for the PowerPC architecture.
virtual Base::Ptr clone() const
Creates a new copy of a disassembler.
const Sawyer::BitFlags< PowerpcCapability > & capabilities() const
Capabilities describe what instructions can be decoded.
Sawyer::BitFlags< PowerpcCapability > & capabilities()
Capabilities describe what instructions can be decoded.
bool strictReserved() const
Property: Whether to enforce reserved instruction fields.
void strictReserved(bool)
Property: Whether to enforce reserved instruction fields.
static Ptr instance(const Architecture::BaseConstPtr &)
Allocating constructor for 32- or 64-bit disassembler.
virtual SgAsmInstruction * makeUnknownInstruction(const Exception &)
Makes an unknown instruction from an exception.
virtual SgAsmInstruction * disassembleOne(const MemoryMap::Ptr &map, Address start_va, AddressSet *successors=NULL)
This is the lowest level disassembly function and is implemented in the architecture-specific subclas...
Stores a vector of enum bit flags.
Reference-counting intrusive smart pointer.
Base class for expressions.
Base class for machine instructions.
Base class for integer values.
Reference to memory locations.
Represents one PowerPC machine instruction.
Base class for references to a machine register.
Base class for binary types.
std::shared_ptr< const Base > BaseConstPtr
Reference counted pointer for Architecture::Base.
std::uint64_t Address
Address.
PowerpcCapability
Subsets for the PowerPC instruction set.