Description
Disassembler for the PowerPC architecture.
Definition at line 23 of file Disassembler/Powerpc.h.
#include <Rose/BinaryAnalysis/Disassembler/Powerpc.h>
Public Types | |
| using | Ptr = PowerpcPtr |
| Reference counting pointer. | |
 Public Types inherited from Rose::BinaryAnalysis::Disassembler::Base | |
| using | Ptr = BasePtr |
Public Member Functions | |
| virtual Base::Ptr | clone () const |
| Creates a new copy of a disassembler. | |
| virtual SgAsmInstruction * | disassembleOne (const MemoryMap::Ptr &map, rose_addr_t start_va, AddressSet *successors=NULL) |
| This is the lowest level disassembly function and is implemented in the architecture-specific subclasses. | |
| virtual void | assembleOne (SgAsmInstruction *, SgUnsignedCharList &) |
| virtual SgAsmInstruction * | makeUnknownInstruction (const Exception &) |
| Makes an unknown instruction from an exception. | |
| bool | strictReserved () const |
| Property: Whether to enforce reserved instruction fields. | |
| void | strictReserved (bool) |
| Property: Whether to enforce reserved instruction fields. | |
| const Sawyer::BitFlags< PowerpcCapability > & | capabilities () const |
| Capabilities describe what instructions can be decoded. | |
| Sawyer::BitFlags< PowerpcCapability > & | capabilities () |
| Capabilities describe what instructions can be decoded. | |
| Public Member Functions inherited from Rose::BinaryAnalysis::Disassembler::Base | |
| Architecture::BaseConstPtr | architecture () const |
| Property: Architecture. | |
| virtual const std::string & | name () const |
| Property: Name. | |
| virtual size_t | bytesPerWord () const |
| Property: Bytes per word for the architecture. | |
| virtual ByteOrder::Endianness | byteOrder () const |
| Property: Byte order of memory. | |
| Unparser::BasePtr | unparser () const |
| Unparser. | |
| size_t | instructionAlignment () const |
| Property: Instruction alignment requirement. | |
| SgAsmInstruction * | disassembleOne (const unsigned char *buf, rose_addr_t buf_va, size_t buf_size, rose_addr_t start_va, AddressSet *successors=NULL) |
| Similar in functionality to the disassembleOne method that takes a MemoryMap argument, except the content buffer is mapped 1:1 to virtual memory beginning at the specified address. | |
| void | mark_referenced_instructions (SgAsmInterpretation *, const MemoryMap::Ptr &, const InstructionMap &) |
| Marks parts of the file that correspond to instructions as having been referenced. | |
| AddressSet | get_block_successors (const InstructionMap &, bool &complete) |
| Calculates the successor addresses of a basic block and adds them to a successors set. | |
| size_t | wordSizeBytes () const |
| RegisterDictionaryPtr | registerDictionary () const |
| virtual RegisterDescriptor | instructionPointerRegister () const |
| virtual RegisterDescriptor | stackPointerRegister () const |
| virtual RegisterDescriptor | stackFrameRegister () const |
| virtual RegisterDescriptor | stackSegmentRegister () const |
| virtual RegisterDescriptor | callReturnRegister () const |
| Public Member Functions inherited from Sawyer::SharedObject | |
| SharedObject () | |
| Default constructor. | |
| SharedObject (const SharedObject &) | |
| Copy constructor. | |
| virtual | ~SharedObject () |
| Virtual destructor. | |
| SharedObject & | operator= (const SharedObject &) |
| Assignment. | |
Static Public Member Functions | |
| static Ptr | instance (const Architecture::BaseConstPtr &) |
| Allocating constructor for 32- or 64-bit disassembler. | |
| Static Public Member Functions inherited from Rose::BinaryAnalysis::Disassembler::Base | |
| static SgAsmInstruction * | find_instruction_containing (const InstructionMap &insns, rose_addr_t va) |
| Finds the highest-address instruction that contains the byte at the specified virtual address. | |
Protected Member Functions | |
| Powerpc (const Architecture::BaseConstPtr &) | |
| Protected Member Functions inherited from Rose::BinaryAnalysis::Disassembler::Base | |
| Base (const Architecture::BaseConstPtr &) | |
Additional Inherited Members | |
| Protected Attributes inherited from Rose::BinaryAnalysis::Disassembler::Base | |
| RegisterDescriptor | REG_IP |
| RegisterDescriptor | REG_SP |
| RegisterDescriptor | REG_SS |
| RegisterDescriptor | REG_SF |
| RegisterDescriptor | REG_LINK |
| Register descriptors initialized during construction. | |
| size_t | instructionAlignment_ = 1 |
| Positive alignment constraint for instruction addresses. | |
Member Typedef Documentation
◆ Ptr
Reference counting pointer.
Definition at line 26 of file Disassembler/Powerpc.h.
Constructor & Destructor Documentation
◆ ~Powerpc()
|
inlinevirtual |
Definition at line 59 of file Disassembler/Powerpc.h.
Member Function Documentation
◆ strictReserved() [1/2]
| bool Rose::BinaryAnalysis::Disassembler::Powerpc::strictReserved | ( | ) | const |
Property: Whether to enforce reserved instruction fields.
If this property is true, then any instruction that has a reserved field that is not zero will be treated as an invalid instruction.
◆ strictReserved() [2/2]
| void Rose::BinaryAnalysis::Disassembler::Powerpc::strictReserved | ( | bool | ) |
Property: Whether to enforce reserved instruction fields.
If this property is true, then any instruction that has a reserved field that is not zero will be treated as an invalid instruction.
◆ clone()
|
virtual |
Creates a new copy of a disassembler.
The new copy has all the same settings as the original.
Thread safety: The thread safety of this virtual method depends on the implementation in the subclass.
Implements Rose::BinaryAnalysis::Disassembler::Base.
◆ disassembleOne()
|
virtual |
This is the lowest level disassembly function and is implemented in the architecture-specific subclasses.
It disassembles one instruction at the specified virtual address. The map is a mapping from virtual addresses to buffer and enables instructions to span file segments that are mapped contiguously in virtual memory by the loader but which might not be contiguous in the file. The instruction's successor virtual addresses are added to the optional successor set (note that successors of an individual instruction can also be obtained via Architecture::Base::getSuccessors). If the instruction cannot be disassembled then an exception is thrown and the successors set is not modified.
Thread safety: The safety of this method depends on its implementation in the subclass. In any case, no other thread can be modifying the MemoryMap or successors set at the same time.
Implements Rose::BinaryAnalysis::Disassembler::Base.
◆ assembleOne()
|
inlinevirtual |
Definition at line 62 of file Disassembler/Powerpc.h.
◆ makeUnknownInstruction()
|
virtual |
Makes an unknown instruction from an exception.
Thread safety: The safety of this method depends on its implementation in the subclass.
Implements Rose::BinaryAnalysis::Disassembler::Base.
◆ capabilities() [1/2]
| const Sawyer::BitFlags< PowerpcCapability > & Rose::BinaryAnalysis::Disassembler::Powerpc::capabilities | ( | ) | const |
Capabilities describe what instructions can be decoded.
The decoder capability set describes what subsets of the PowerPC complete instruction set can be decoded. Machine instructions that fall outside the selected subset(s) are decoded as "unknown" instructions.
◆ capabilities() [2/2]
| Sawyer::BitFlags< PowerpcCapability > & Rose::BinaryAnalysis::Disassembler::Powerpc::capabilities | ( | ) |
Capabilities describe what instructions can be decoded.
The decoder capability set describes what subsets of the PowerPC complete instruction set can be decoded. Machine instructions that fall outside the selected subset(s) are decoded as "unknown" instructions.
The documentation for this class was generated from the following file:
